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* ARM: vexpress: Start using new Versatile Express infrastructurePawel Moll2012-11-051-27/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch starts using all the configuration infrastructure. - generic GPIO library is forced now - sysreg GPIOs are used as MMC CD and WP information sources; thanks to this MMCI auxiliary data is not longer necessary - DVI muxer and mode control is removed from non-DT V2P-CA9 code as this is now handled by the vexpress-dvi driver - clock generators control is removed as is being handled by the common clock driver now - the sysreg and sysctl control is now delegated to the appropriate drivers and all related code was removed - NOR Flash set_vpp function has been removed as the control bit used does _not_ control its VPP line, but the #WP signal instead (which is de facto unusable in case of Linux MTD drivers); this also allowed the remove its DT auxiliary data The non-DT code defines only minimal required number of the config devices. Device Trees are updated to make use of all new features. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* Merge tag 'multi-platform-for-3.7' of git://sources.calxeda.com/kernel/linux ↵Olof Johansson2012-09-201-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/multiplatform Enable initial ARM multi-platform support for highbank, mvebu, socfpga, picoxcell, and vexpress. Multi-platform support is dependent on mach/gpio.h removal and restructuring of DEBUG_LL and dtb build rules included in this branch. This has been built for all defconfigs, and booted on highbank with all 5 platforms enabled. By Rob Herring (18) and Arnd Bergmann (1) via Rob Herring * tag 'multi-platform-for-3.7' of git://sources.calxeda.com/kernel/linux: ARM: vexpress: convert to multi-platform ARM: initial multiplatform support ARM: mvebu: move armada-370-xp.h in mach dir ARM: vexpress: remove dependency on mach/* headers ARM: picoxcell: remove dependency on mach/* headers ARM: move all dtb targets out of Makefile.boot ARM: picoxcell: move debug macros to include/debug ARM: socfpga: move debug macros to include/debug ARM: mvebu: move debug macros to include/debug ARM: vexpress: move debug macros to include/debug ARM: highbank: move debug macros to include/debug ARM: move debug macros to common location ARM: make mach/gpio.h headers optional ARM: orion: move custom gpio functions to orion-gpio.h ARM: shmobile: move custom gpio functions to sh-gpio.h ARM: pxa: use gpio_to_irq for sharppm_sl net: pxaficp_ir: add irq resources usb: pxa27x_udc: remove IRQ_USB define staging: ste_rmi4: remove gpio.h include Conflicts due to addition of bcm2835 and removal of pnx4008 in: arch/arm/Kconfig arch/arm/Makefile Conflicts due to new dtb targets, moved to arch/arm/boot/dts/Makefile in: arch/arm/mach-imx/Makefile.boot arch/arm/mach-mxs/Makefile.boot arch/arm/mach-tegra/Makefile.boot Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: vexpress: remove dependency on mach/* headersArnd Bergmann2012-09-141-0/+1
| | | | | | | | | | Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Pawel Moll <pawel.moll@arm.com>
* | ARM: pmu: remove arm_pmu_type enumerationSudeep KarkadaNagesha2012-08-231-2/+1
|/ | | | | | | | | | | | | | | | | | | | | | | The arm_pmu_type enumeration was initially introduced to identify different PMU types in the system, the usual one being that on the CPU (ARM_PMU_DEVICE_CPU). With the removal of the PMU reservation code and the introduction of devicetree bindings for the CPU PMU, the enumeration is no longer required. This patch removes the enumeration and updates the various CPU PMU platform devices so that they no longer pass an .id field referring to identify the PMU type. Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Pawel Moll <pawel.moll@arm.com> Acked-by: Jon Hunter <jon-hunter@ti.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> [will: cosmetic edits and actual removal of the enum type] Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: vexpress: Initial common clock supportPawel Moll2012-07-131-45/+10
| | | | | | | | | | | | | | This patch makes Versatile Express use the common clock framework instead of the plat-versatile implementation. It defines clock provider for VE's OSCs (clock generators) and registers all required fixed and variable clock sources (for both motherboard and core tile). This is a simple conversion of the existing state and will be extended (and migrated to drivers/clk) in the near future. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* ARM: vexpress: Check master site in daughterboard's sysctl operationsPawel Moll2012-07-121-3/+12
| | | | | | | | | | | With recent enough motherboard firmware, core tile can be fitted in either of the two daughterboard sites. The non-DT tile code for V2P-CA9 did not check that when configuring DVI output nor setting CLCD pixel clock. Fixed now, providing "get master site" API in motherboard's code. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* Merge branch 'tegra/cleanups' into next/timerArnd Bergmann2012-03-211-4/+4
|\ | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-tegra/Makefile arch/arm/mach-vexpress/core.h The tegra Makefile was changed in four different branches in the same line. This merge should reduce the amount of churn. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * Merge tag 'v3.3-rc2' into depends/rmk/for-armsocOlof Johansson2012-02-071-2/+2
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | There were conflicts between fixes going in after 3.3-rc1 and Russell's stable arm-soc base branch. Resolving it in the dependency branch so that each topic branch shares the same resolution. Conflicts: arch/arm/mach-at91/at91cap9.c arch/arm/mach-at91/at91sam9g45.c
| * | ARM: amba: vexpress: get rid of private platform amba_device initializerRussell King2012-01-251-4/+4
| | | | | | | | | | | | | | | Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: plat-versatile: convert to twd_local_timer_register() interfaceMarc Zyngier2012-03-131-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the new smp_twd runtime registration interface to the RealView/VE platforms, and remove the old compile-time support. Tested on EB11MP. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | | ARM: vexpress: Get rid of MMIO_P2VPawel Moll2012-02-231-39/+19
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the MMIO_P2V and __MMIO_P2V macros, defining constant virtual base for motherboard and tile peripherals instead. Additionally, in preparation for the new motherboard memory map, the motherboard peripherals are using base pointers calculated in runtime, instead of compile-time calculated values. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
* | ARM: vexpress: fix two section mismatch warningsRussell King2012-01-191-2/+2
|/ | | | | | | | | | | | WARNING: vmlinux.o(.text+0x1bc9c): Section mismatch in reference from the function ct_ca9x4_init_cpu_map() to the function .init.text:scu_get_core_count() The function ct_ca9x4_init_cpu_map() references the function __init scu_get_core_count(). WARNING: vmlinux.o(.text+0x1bce8): Section mismatch in reference from the function ct_ca9x4_init_cpu_map() to the function .init.text:set_smp_cross_call() The function ct_ca9x4_init_cpu_map() references the function __init set_smp_cross_call(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: smp: fix clipping of number of CPUsRussell King2011-10-201-0/+6
| | | | | | | | | | Rather than clipping the number of CPUs using the compile-time NR_CPUS constant, use the runtime nr_cpu_ids value instead. This allows the nr_cpus command line option to work as expected. Cc: <stable@kernel.org> Reported-by: Mark Salter <msalter@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6993/1: platsmp: Allow secondary cpu hotplug with maxcpus=1Stephen Boyd2011-07-071-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | If an ARM system has multiple cpus in the same socket and the kernel is booted with maxcpus=1, secondary cpus are possible but not present due to how platform_smp_prepare_cpus() is called. Since most typical ARM processors don't actually support physical hotplug, initialize the present map to be equal to the possible map in generic ARM SMP code. Also, always call platform_smp_prepare_cpus() as long as max_cpus is non-zero (0 means no SMP) to allow platform code to do any SMP setup. After applying this patch it's possible to boot an ARM system with maxcpus=1 on the command line and then hotplug in secondary cpus via sysfs. This is more in line with how x86 does things. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: David Brown <davidb@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*-. Merge branches 'consolidate-clksrc', 'consolidate-flash', ↵Russell King2011-05-231-0/+2
|\ \ | | | | | | | | | 'consolidate-generic', 'consolidate-smp', 'consolidate-stmp' and 'consolidate-zones' into consolidate
| | * ARM: consolidate SMP cross call implementationRussell King2011-05-231-0/+2
| |/ | | | | | | | | | | | | | | Rather than having each platform class provide a mach/smp.h header for smp_cross_call(), arrange for them to register the function with the core ARM SMP code instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | clockevents: ARM sp804: obtain sp804 timer rate via clksRussell King2011-05-231-0/+4
| | | | | | | | | | | | | | | | | | This allows platforms to specify the rate of the SP804 clockevent via the clk subsystem. While ARM boards clock these at 1MHz, BCMRing also has SP804 timers but are clocked at different rates. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | clockevents: ARM sp804: allow clockevent name to be specifiedRussell King2011-05-231-1/+2
| | | | | | | | | | | | | | This allows platforms to specify the clcokevent name upon registration. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | clocksource: ARM sp804: obtain sp804 timer rate via clksRussell King2011-05-231-0/+8
| | | | | | | | | | | | | | | | | | This allows platforms to specify the rate of the SP804 clocksource via the clk subsystem. While ARM boards clock these at 1MHz, BCMRing also has SP804 timers but are clocked at different rates. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | clocksource: ARM sp804: allow clocksource name to be specifiedRussell King2011-05-231-1/+1
|/ | | | | | | | | This allows platforms to specify the clocksource name upon registration, which is necessary should they wish to register more than one sp804 clocksource. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6771/1: vexpress: add support for multiple core tilesWill Deacon2011-03-201-15/+30
| | | | | | | | | | | | | | The current Versatile Express BSP defines the MACHINE_START macro in the core tile code. This patch moves this into the generic board code and introduces a method for determining the current tile at runtime, allowing the Kernel to have support for multiple tiles compiled in. Tile-specific functions are executed via a descriptor struct containing the correct implementations for the current tile. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
*---. Merge branches 'fixes', 'pgt-next' and 'versatile' into develRussell King2011-03-201-51/+17
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| | | * ARM: vexpress: use new init_early for clock tree and sched_clock initRussell King2011-02-191-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the clock tree and our sched_clock() early. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * ARM: vexpress: switch Versatile Express to use consolidated CLCDRussell King2011-02-191-49/+9
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | This switches Versatile Express to use the conslidated CLCD panel support, including the display capabilities. As Versatile Express uses a PL111, it can support the full range of pixel formats - 444, 5551, 565 in both RGB and BGR mode. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: P2V: avoid initializers and assembly using PHYS_OFFSETRussell King2011-02-171-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | As PHYS_OFFSET will be becoming a variable, we can't have it used in initializers nor assembly code. Replace those in generic code with a run-time initialization. Replace those in platform code using the individual platform specific PLAT_PHYS_OFFSET. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: David Brown <davidb@codeaurora.org> Acked-by: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'misc' into develRussell King2011-01-061-2/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/common/Makefile arch/arm/kernel/Makefile arch/arm/kernel/smp.c
| * \ Merge branch 'smp' into miscRussell King2011-01-061-0/+2
| |\ \ | | |/ | | | | | | | | | | | | Conflicts: arch/arm/kernel/entry-armv.S arch/arm/mm/ioremap.c
| * | ARM: 6483/1: arm & sh: factorised duplicated clkdev.cJean-Christop PLAGNIOL-VILLARD2010-11-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | factorise some generic infrastructure to assist looking up struct clks for the ARM & SH architecture. as the code is identical at 99% put the arch specific code for allocation as example in asm/clkdev.h Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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*---. \ \ Merge branches 'ftrace', 'gic', 'io', 'kexec', 'mod', 'sa11x0', 'sh' and ↵Russell King2011-01-051-6/+3
|\ \ \ \ \ | | | |/ / | | |/| / | |_|_|/ |/| | | 'versatile' into devel
| | | * ARM: 6432/1: move timer-sp.c from versatile to commonRob Herring2010-11-041-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Rob Herring <rob.herring@smooth-stone.com> The timer-sp h/w used on versatile platforms can also be used for other platforms, so move it to a common location. Signed-off-by: Rob Herring <rob.herring@smooth-stone.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: GIC: consolidate gic_cpu_base_addr to common GIC codeRussell King2010-12-141-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: GIC: provide a single initialization function for boot CPURussell King2010-12-141-2/+1
|/ / | | | | | | | | | | | | | | | | Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6472/1: vexpress ct-ca9x4: only set twd_base if local timers are being usedWill Deacon2010-11-101-0/+2
|/ | | | | | | | | | | | | In commit bde28b84, I made the assumption that CONFIG_SMP is always set for the quad-core ct-ca9x4 platform. As it turns out, people who aren't using the SMP goodness are confronted with a build failure. This patch fixes this issue by ensure that twd_base is only set if local timers are being used (and therefore SMP support is configured). Reported-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm: remove machine_desc.io_pg_offst and .phys_ioNicolas Pitre2010-10-201-2/+0
| | | | | | | | | | | | | | | Since we're now using addruart to establish the debug mapping, we can remove the io_pg_offst and phys_io members of struct machine_desc. The various declarations were removed using the following script: grep -rl MACHINE_START arch/arm | xargs \ sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }' [ Initial patch was from Jeremy Kerr, example script from Russell King ] Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Eric Miao <eric.miao at canonical.com>
* ARM: fix section mismatch warnings in Versatile ExpressRussell King2010-10-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WARNING: vmlinux.o(.text+0xbf30): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clocksource_init() The function v2m_timer_init() references the function __init sp804_clocksource_init(). This is often because v2m_timer_init lacks a __init annotation or the annotation of sp804_clocksource_init is wrong. WARNING: vmlinux.o(.text+0xbf3c): Section mismatch in reference from the function v2m_timer_init() to the function .init.text:sp804_clockevents_init() The function v2m_timer_init() references the function __init sp804_clockevents_init(). This is often because v2m_timer_init lacks a __init annotation or the annotation of sp804_clockevents_init is wrong. WARNING: vmlinux.o(.text+0xc524): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:l2x0_init() The function ct_ca9x4_init() references the function __init l2x0_init(). This is often because ct_ca9x4_init lacks a __init annotation or the annotation of l2x0_init is wrong. WARNING: vmlinux.o(.text+0xc530): Section mismatch in reference from the function ct_ca9x4_init() to the function .init.text:clkdev_add_table() The function ct_ca9x4_init() references the function __init clkdev_add_table(). This is often because ct_ca9x4_init lacks a __init annotation or the annotation of clkdev_add_table is wrong. WARNING: vmlinux.o(.text+0xc578): Section mismatch in reference from the function ct_ca9x4_init() to the (unknown reference) .init.data:(unknown) The function ct_ca9x4_init() references the (unknown reference) __initdata (unknown). This is often because ct_ca9x4_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Fix these by making ct_ca9x4_init() and v2m_timer_init() both __init. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6411/1: vexpress: set RAM latencies to 1 cycle for PL310 on ct-ca9x4 tileWill Deacon2010-09-271-1/+7
| | | | | | | | | | | | | | | The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr ↵Catalin Marinas2010-09-171-1/+1
| | | | | | | | | | | | | | | | | | | register Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: <stable@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6218/1: Versatile Express: add support for local timers on CA9X4 ↵Will Deacon2010-07-091-0/+2
| | | | | | | | | | daughterboard This patch adds support for the Cortex-A9 local timers available when using the CA9X4 daughterboard with the Versatile Express. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-011-1/+2
| | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm: update gfp/slab.h includesTejun Heo2010-06-281-0/+1
| | | | | | | | | | Implicit slab.h inclusion via percpu.h is about to go away. Make sure gfp.h or slab.h is included as necessary. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
* ARM: 6057/1: Realview: register PMU IRQs during board initialisationWill Deacon2010-05-021-0/+34
| | | | | | | | | This patch updates the initialisation routines for the Realview boards and the Versatile Express board [ca9x4 tile] so that they register their PMU IRQs with the PMU framework in the Kernel. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Add Versatile Express CA9x4 processor supportRussell King2010-05-021-0/+215
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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