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* ARM: tegra20: Store CPU "resettable" status in IRAMDmitry Osipenko2015-05-041-3/+7
| | | | | | | | | | | | | | | | | Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed tegra_resume() location storing from late to early and, as a result, broke suspend on Tegra20. PMC scratch register 41 is used by tegra LP1 resume code for retrieving stored physical memory address of common resume function and in the same time used by tegra20_cpu_shutdown() (shared by Tegra20 cpuidle driver and platform SMP code), which is storing CPU1 "resettable" status. It implies strict order of scratch register usage, otherwise resume function address is lost on Tegra20 after disabling non-boot CPU's on suspend. Fix it by storing "resettable" status in IRAM instead of PMC scratch register. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver) Cc: <stable@vger.kernel.org> # v3.17+ Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Re-add removed SoC id macro to tegra_resume()Dmitry Osipenko2014-11-171-0/+1
| | | | | | | | | | | | | | | | Commit d127e9c ("ARM: tegra: make tegra_resume can work with current and later chips") removed tegra_get_soc_id macro leaving used cpu register corrupted after branching to v7_invalidate_l1() and as result causing execution of unintended code on tegra20. Possibly it was expected that r6 would be SoC id func argument since common cpu reset handler is setting r6 before branching to tegra_resume(), but neither tegra20_lp1_reset() nor tegra30_lp1_reset() aren't setting r6 register before jumping to resume function. Fix it by re-adding macro. Fixes: d127e9c (ARM: tegra: make tegra_resume can work with current and later chips) Cc: <stable@vger.kernel.org> # v3.13+ Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Use a function to get the chip IDThierry Reding2014-07-171-1/+2
| | | | | | | | | | | Instead of using a simple variable access to get at the Tegra chip ID, use a function so that we can run additional code. This can be used to determine where the chip ID is being accessed without being available. That in turn will be handy for resolving boot sequence dependencies in order to convert more code to regular initcalls rather than a sequence fixed by Tegra SoC setup code. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: tegra: Sort includes alphabeticallyThierry Reding2014-07-171-2/+2
| | | | | | | | If these aren't sorted alphabetically, then the logical choice is to append new ones, however that creates a lot of potential for conflicts because every change will then add new includes in the same location. Signed-off-by: Thierry Reding <treding@nvidia.com>
* ARM: l2c: tegra: convert to common l2c310 early resume functionalityRussell King2014-05-301-8/+3
| | | | | | | Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: tegra: make tegra_resume can work with current and later chipsJoseph Lo2013-10-181-8/+5
| | | | | | | | | | | Because the CPU0 was the first up and the last down core when cluster power up/down or platform suspend. So only CPU0 needs the rest of the functions to reset flow controller and re-enable SCU and L2. We also move the L2 init function for Cortex-A15 to there. The secondery CPU can just call cpu_resume. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add common resume handling code for LP1 resumingJoseph Lo2013-08-121-0/+13
| | | | | | | | | | | | | | Add support to the Tegra CPU reset vector to detect whether the CPU is resuming from LP1 suspend state. If it is, branch to the LP1-specific resume code. When Tegra enters the LP1 suspend state, the SDRAM controller is placed into a self-refresh state. For this reason, we must place the LP1 resume code into IRAM, so that it is accessible before SDRAM access has been re-enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15Joseph Lo2013-07-191-0/+1
| | | | | | | | | | When there is a cluster power down cycle in suspend, we need to set up the correct L2 RAM data RAM latency to make L2 cache work correctly. This is only needed for cluster 0 and needs to be done in tegra_resume before the cache is enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9Joseph Lo2013-07-191-2/+5
| | | | | | | | | The v7_invalidate_l1 was used for the L1 cache that come out from reset in a undefined state. This is no need for Cortex-A15. We do it for A9 only. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: remove ifdef in the tegra_resumeJoseph Lo2013-06-051-3/+1
| | | | | | | | | | | | | | | | | The ifdef was originally added with the intent that the runtime SoC detection code, and code to support SoCs other than Tegra20, was only included if the kernel supported SoCs other than Tegra20. However, the condition was somewhat backwards and did not achieve this goal. Simply remove the ifdef to solve this, rather than creating a much more complex version. We also fix a typo that caused a build error due to cpu_to_csr_req being undefined. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren: rewrote commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra114: add CPU hotplug supportJoseph Lo2013-05-221-3/+12
| | | | | | | | | | The Tegra114 is a quad cores SoC. Each core can be hotplugged including CPU0. The hotplug sequence can be controlled by setting event trigger in flow controller. Then the flow controller will take care all the power sequence that include CPU up and down. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: make tegra_resume can work for Tegra114Joseph Lo2013-05-221-4/+9
| | | | | | | | | | | Tegra114 had a newer flow controller hardware that makes its behavior and configurations are different with other Tegra series. We fix the common resume function of tegra_resume to make it can work on Tegra114 by checking SoC ID. And also checking CPU primary part number to isolate the support code for Cortex A9 and A15. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add an assembly marco to check Tegra SoC IDJoseph Lo2013-05-221-16/+9
| | | | | | | | | | There are some Tegra SoC ID checking code around the low level assembly code. Adding a marco to replace them. For the single image to support all the Tegra series, we may also need the marco in other common code. So we make it become a marco for the usage. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: fix relocation truncated error when THUMB2_KERNEL enabledJoseph Lo2013-04-181-0/+1
| | | | | | | | | | | | | | | | | | | The conditional branch instruction in Thumb2 only available to short range. The linker will fail when the conditional branch over the range. Then resulting in link error when generating kernel image. e.g.: arch/arm/mach-tegra/reset-handler.S:47:(.text+0xf8e): relocation truncated to fit: R_ARM_THM_JUMP19 against symbol `cpu_resume' defined in .data section in arch/arm/kernel/built-in.o This patch using a Thumb2 instruction IT (if-then) to have a longer branch range. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: tegra: don't unlock MMIO access to DBGLARJoseph Lo2013-03-111-3/+0
| | | | | | | | | | | | | | | There is no need to unlock MMIO access to the DBGLAR all the time. Doing so may even cause problems if a SW bug causes writes to that MMIO region. Cortex-A15 processors do not support the CP14 register write the code currently uses to unlock the DBGLAR; the instruction throws an undefined instruction exceptions. This prevents tegra_secondary_startup() from executing on Tegra114, and hence prevents SMP. Remove the code that unlocks this access. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: add CPU errata WARs to Tegra reset handlerStephen Warren2013-03-111-6/+39
| | | | | | | | | | | | | | | | | | | | | | | | | The CPU cores in Tegra contain some errata. Workarounds must be applied for these every time a CPU boots. Implement those workarounds directly in the Tegra-specific CPU reset vector. Many of these workarounds duplicate code in the core ARM kernel. However, the core ARM kernel cannot enable those workarounds when building a multi-platform kernel, since they require writing to secure- only registers, and a multi-platform kernel often does not run in secure mode, and also cannot generically/architecturally detect whether it is running in secure mode, and hence cannot either unconditionally or conditionally apply these workarounds. Instead, the workarounds must be applied in architecture-specific reset code, which is able to have more direct knowledge of the secure/normal state. On Tegra, we will be able to detect this using a non-architected register in the future, although we currently assume the kernel runs only in secure mode. Other SoCs may never run the kernel in secure mode, and hence always rely on a secure monitor to enable the workarounds, and hence never implement them in the kernel. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: make device can run on UPJoseph Lo2013-01-281-0/+239
The reset handler code is used for either UP or SMP. To make Tegra device can compile for UP. It needs to be moved to another file that is not SMP only. This is because the reset handler also be needed by CPU idle "powered-down" mode. So we also need to put the reset handler init function in non-SMP only and init them always. And currently the implementation of the reset handler to know which CPU is OK to bring up was identital with "cpu_present_mask". But the "cpu_present_mask" did not initialize yet when the reset handler init function was moved to init early function. We use the "cpu_possible_mask" to replace "cpu_present_mask". Then it can work on both UP and SMP case. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren: dropped the move of v7_invalidate_l1() from one file to another, to avoid conflicts with Pavel's cleanup of this function, adjust Makefile so each line only contains 1 file.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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