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* ARM: PXA2xx: MFP: fix potential direction bugIgor Grinberg2012-04-271-0/+9
| | | | | | | | | | | | | | | | | | | Pins configured as input and have MFP_LPM_DRIVE_* flag set, can have a wrong output value for some period of time (spike) during the suspend sequence. This can happen because the direction of the pins (GPDR) is set by software and the output level is set by hardware (PGSR) at a later stage. Fix the above potential bug by setting the output levels first. Also save the actual levels of the pins before the suspend and restore them after the resume, but before the direction settings take place, so the same bug as described above will not happen in the resume sequence. Reported-by: Paul Parsons <lost.distance@yahoo.com> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Tested-by: Paul Parsons <lost.distance@yahoo.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* ARM: PXA2xx: MFP: fix bug with MFP_LPM_KEEP_OUTPUTIgor Grinberg2012-04-271-2/+10
| | | | | | | | | | | | | | | Pins that have MFP_LPM_KEEP_OUTPUT set and are configured for output must retain the output state in low power mode. Currently, the pin direction configuration is overrided with values in gpdr_lpm[] array and do not obey the MFP_LPM_KEEP_OUTPUT setting. Fix the above bug and add some documentation to clarify the MFP_LPM_KEEP_OUTPUT setting purpose. Reported-by: Paul Parsons <lost.distance@yahoo.com> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Tested-by: Paul Parsons <lost.distance@yahoo.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* Merge tag 'cleanup2' of ↵Linus Torvalds2012-03-291-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull "ARM: cleanups of io includes" from Olof Johansson: "Rob Herring has done a sweeping change cleaning up all of the mach/io.h includes, moving some of the oft-repeated macros to a common location and removing a bunch of boiler plate. This is another step closer to a common zImage for multiple platforms." Fix up various fairly trivial conflicts (<mach/io.h> removal vs changes around it, tegra localtimer.o is *still* gone, yadda-yadda). * tag 'cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits) ARM: tegra: Include assembler.h in sleep.S to fix build break ARM: pxa: use common IOMEM definition ARM: dma-mapping: convert ARCH_HAS_DMA_SET_COHERENT_MASK to kconfig symbol ARM: __io abuse cleanup ARM: create a common IOMEM definition ARM: iop13xx: fix missing declaration of iop13xx_init_early ARM: fix ioremap/iounmap for !CONFIG_MMU ARM: kill off __mem_pci ARM: remove bunch of now unused mach/io.h files ARM: make mach/io.h include optional ARM: clps711x: remove unneeded include of mach/io.h ARM: dove: add explicit include of dove.h to addr-map.c ARM: at91: add explicit include of hardware.h to uncompressor ARM: ep93xx: clean-up mach/io.h ARM: tegra: clean-up mach/io.h ARM: orion5x: clean-up mach/io.h ARM: davinci: remove unneeded mach/io.h include [media] davinci: remove includes of mach/io.h ARM: OMAP: Remove remaining includes for mach/io.h ARM: msm: clean-up mach/io.h ...
| * ARM: pxa: use common IOMEM definitionRob Herring2012-03-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pxa was missed in the moving of IOMEM to a common definition, so lots of IOMEM redefined warnings were introduced. So remove pxa IOMEM definition and fix all the fallout. Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Eric Miao <eric.y.miao@gmail.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Haojian Zhuang <haojian.zhuang@marvell.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.de> Cc: rtc-linux@googlegroups.com Cc: alsa-devel@alsa-project.org
* | ARM: pxa: fix invalid mfp pin issueHaojian Zhuang2012-03-061-0/+7
|/ | | | | | | | | | | | | | | | | | | | | | | Failure is reported on hx4700 with kernel v3.3-rc1. __mfp_validate: GPIO20 is invalid pin __mfp_validate: GPIO21 is invalid pin __mfp_validate: GPIO15 is invalid pin __mfp_validate: GPIO78 is invalid pin __mfp_validate: GPIO79 is invalid pin __mfp_validate: GPIO80 is invalid pin __mfp_validate: GPIO33 is invalid pin __mfp_validate: GPIO48 is invalid pin __mfp_validate: GPIO49 is invalid pin __mfp_validate: GPIO50 is invalid pin Since pxa_last_gpio is used in mfp-pxa2xx driver. But it's only updated in pxa-gpio driver that run after mfp-pxa2xx driver. So update the pxa_last_gpio first in mfp-pxa2xx driver. Reported-by: Paul Parsons <lost.distance@yahoo.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
* ARM: pxa: change gpio to platform deviceHaojian Zhuang2011-11-151-1/+5
| | | | | | Remove most gpio macros and change gpio driver to platform driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
* ARM: 7104/1: plat-pxa: break out GPIO driver specificsLinus Walleij2011-10-011-0/+1
| | | | | | | | | | | The <mach/gpio.h> file is included from upper directories and deal with generic GPIO and gpiolib stuff. Break out the platform and driver specific defines and functions into its own header file. Cc: Eric Miao <eric.y.miao@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: gpio: convert includes of mach/gpio.h and asm/gpio.h to linux/gpio.hRussell King2011-08-081-2/+1
| | | | | | | | Convert arch/arm includes of mach/gpio.h and asm/gpio.h to linux/gpio.h before we start consolidating the individual platform implementations of the gpio header files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: pxa: fix PGSR register address calculationPaul Parsons2011-07-061-2/+2
| | | | | | | | | | The file mfp-pxa2xx.c defines a macro, PGSR(), which translates a gpio bank number to a PGSR register address. The function pxa2xx_mfp_suspend() erroneously passed in a gpio number instead of a gpio bank number. Signed-off-by: Paul Parsons <lost.distance@yahoo.com> Cc: stable@kernel.org Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* ARM / PXA: Use struct syscore_ops for "core" power managementRafael J. Wysocki2011-04-241-7/+5
| | | | | | | | | | | | | Replace sysdev classes and struct sys_device objects used for "core" power management by the PXA platform code with struct syscore_ops objects that are simpler. This reduces the code size and the kernel memory footprint. It also is necessary for removing sysdevs entirely from the kernel in the future. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
* [ARM] pxa: allow MFP_LPM_INPUT to be explicitly specifiedEric Miao2010-05-111-0/+1
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: allow keypad GPIOs to wakeup when configured as genericEric Miao2010-05-111-9/+22
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add MFP_LPM_KEEP_OUTPUT flag to pin configEric Miao2010-05-111-0/+11
| | | | | | | Some pins are expected to keep their last level during suspend, and introduce MFP_LPM_KEEP_OUTPUT for this. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: enable GPIO receivers after configuring pinsTimothy Clacy2009-05-181-0/+3
| | | | | | | | | | | | | 'mach-pxa' platforms currently rely on a bootloader to setup GPIO pins and clear RDH (to enable inputs). A kernel loaded by a 'minimal' bootloader, that doesn't touch any pins, will not function correctly; inputs will remain disabled, even after the pins are configured. The following change fixes the issue and has been verified on Gumstix Verdex XL6P and a custom PXA270 platform. Signed-off-by: Timothy Clacy <tcl@phaseone.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] pxa: save/restore PGSR on suspend/resume.Daniel Ribeiro2009-05-181-0/+3
| | | | | Signed-off-by: Daniel Ribeiro <drwyrm@gmail.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] pxa: access GPIO registers by chip so to make it further genericEric Miao2009-03-091-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's handle GPIOs by banks, each bank covers up to 32 GPIOs with one set of registers, and each set of registers start from different offsets. GPLR GPDR GPSR GPCR GRER GFER GEDR BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 NOTE: BANK 3 is only available on PXA27x and later processors. BANK 4 and 5 are only available on PXA935 1. introduce GPIO_BANK(n) for the offset base of each bank 2. 'struct pxa_gpio_chip' is expanded to include IRQ edge and mask setings, and saved register values as well, and is dynamically allocated due to possible bank number ranging from 3 to 6 3. all accesses to GPIO registers are made through 'regbase' within 'pxa_gpio_chip', and register offset 4. introduce several inline functions to simplify the code a bit 5. change IRQ demux handler to base on gpio chips Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] pxa: move GPIO register definitions into <mach/gpio.h>Eric Miao2009-03-091-2/+1
| | | | | | | | This makes gpio.c fully independent of pxa-regs.h (except for the virtual address of the registers). Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] pxa: add support for additional GPIOs on PXA26xEric Miao2008-12-021-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Original patch from Marek Vasut, the problems with PXA26x are: 1. there are additional 4 GPIOs 86,87,88,89 have their direction bits inverted in GPDR2, as well as their alternate function bits being '1' for their GPIO functionality in GAFRx 2. there is no easy way to decide if the processor is a pxa26x or a pxa250/pxa255 at run-time, so the assumption here is the pxa26x will be treated as one of the pxa25x variants, and board code should have a better knowledge of the processor it is featured Introduce pxa26x_init_irq() for the second purpose, and treat the additional GPIOs > 85 on PXA25x specially. Kconfig option CONFIG_CPU_PXA26x is introduced to optimize the code a bit when PXA26x support isn't needed. Board config options have to select this to enable the support for PXA26x. __gpio_is_inverted() will be optimized way when CONFIG_CPU_PXA26x isn't selected. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] pxa: use 'pxa_last_gpio' instead of 'gpio_nr' in mfp-pxa2xx.cEric Miao2008-12-021-9/+5
| | | | | | | | | | | | The 'gpio_nr' can really be inferred by 'pxa_last_gpio', and since we already have that variable, remove the unnecessary 'gpio_nr' now. Also, fix the incorrect GPIO number passed in pxa27x_init_irq(). Note: pxa_last_gpio should be initialized earlier, and this is true since it's been assigned in machine_desc->init_irq(). Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] pxa: add muxed gpio wakeup sources on pxa2xx architecturesRobert Jarzmik2008-12-021-2/+29
| | | | | | | | | PXA SoC have several GPIOs muxed on only one wakeup source. Add support for these wakeup sources which were missing in mfp core support. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Eric Miao <eric.miao@marvell.com>
* [ARM] pxa: fix incorrect initialization of mfp sysdev when not pxa2xxEric Miao2008-10-071-0/+3
| | | | | | | | The initialization of mfp sysdev in pxa2xx_mfp_init() shall really be avoided when !cpu_is_pxa2xx(). Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] pxa: better MFP low power state support for pxa25x/pxa27xEric Miao2008-09-261-73/+149
| | | | | | | | | | | | | When configured as a specific low power state: MFP_LPM_DRIVE_LOW, MFP_LPM_DRIVE_HIGH, the corresponding GPDR register bit during low power mode shall be re-configured as output (if they are not configured so), thus the PGSRx bits can output. Create an additional low power values GPDR registers, and properly save/restore the GAFR + GPDR registers when doing suspend/resume. Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-071-4/+4
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] pxa: add pxa2xx_mfp_set_lpm() to facilitate low power state changeEric Miao2008-07-091-14/+37
| | | | | | | | | | Some boards want to change low power state of pins on-the-fly, this function helps to facilitate that operation instead of switching back-n-forth between two configurations with pxa2xx_mfp_config(). Signed-off-by: Eric Miao <eric.miao@marvell.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] pxa: introduce dedicated __mfp_validate() to check PXA2xx MFPEric Miao2008-07-091-6/+14
| | | | | | Signed-off-by: Eric Miao <eric.miao@marvell.com> Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] pxa: separate out power manager and clock registersRussell King2008-06-021-0/+1
| | | | | | | | The power manager and core clock registers aren't present in PXA3 CPUs. Move them out of pxa-regs.h into pxa2xx-regs.h, and include pxa2xx-regs.h where necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] pxa: allow dynamic enable/disable of GPIO wakeup for pxa{25x,27x}eric miao2008-04-191-19/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes include: 1. rename MFP_LPM_WAKEUP_ENABLE into MFP_LPM_CAN_WAKEUP to indicate the board capability of this pin to wakeup the system 2. add gpio_set_wake() and keypad_set_wake() to allow dynamically enable/disable wakeup from GPIOs and keypad GPIO * these functions are currently kept in mfp-pxa2xx.c due to their dependency to the MFP configuration 3. pxa2xx_mfp_config() only gives early warning if MFP_LPM_CAN_WAKEUP is set on incorrect pins So that the GPIO's wakeup capability is now decided by the following: a) processor's capability: (only those GPIOs which have dedicated bits within PWER/PRER/PFER can wakeup the system), this is initialized by pxa{25x,27x}_init_mfp() b) board design decides: - whether the pin is designed to wakeup the system (some of the GPIOs are configured as other functions, which is not intended to be a wakeup source), by OR'ing the pin config with MFP_LPM_CAN_WAKEUP - which edge the pin is designed to wakeup the system, this may depends on external peripherals/connections, which is totally board specific; this is indicated by MFP_LPM_EDGE_* c) the corresponding device's (most likely the gpio_keys.c) wakeup attribute: Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] pxa: add MFP-alike pin configuration support for pxa{25x, 27x}eric miao2008-04-191-0/+190
Pin configuration on pxa{25x,27x} has now separated from generic GPIO into dedicated mfp-pxa2xx.c by this patch. The name "mfp" is borrowed from pxa3xx and is used here to alert the difference between the two concepts: pin configuration and generic GPIOs. A GPIO can be called a "GPIO" _only_ when the corresponding pin is configured so. A pin configuration on pxa{25x,27x} is composed of: - alternate function selection (or pin mux as commonly called) - low power state or sleep state - wakeup enabling from low power mode The following MFP_xxx bit definitions in mfp.h are re-used: - MFP_PIN(x) - MFP_AFx - MFP_LPM_DRIVE_{LOW, HIGH} - MFP_LPM_EDGE_* Selecting alternate function on pxa{25x, 27x} involves configuration of GPIO direction register GPDRx, so a new bit and MFP_DIR_{IN, OUT} are introduced. And pin configurations are defined by the following two macros: - MFP_CFG_IN : for input alternate functions - MFP_CFG_OUT : for output alternate functions Every configuration should provide a low power state if it configured as output using MFP_CFG_OUT(). As a general guideline, the low power state should be decided to minimize the overall power dissipation. As an example, it is better to drive the pin as high level in low power mode if the GPIO is configured as an active low chip select. Pins configured as GPIO are defined by MFP_CFG_IN(). This is to avoid side effects when it is firstly configured as output. The actual direction of the GPIO is configured by gpio_direction_{input, output} Wakeup enabling on pxa{25x, 27x} is actually GPIO based wakeup, thus the device based enable_irq_wake() mechanism is not applicable here. E.g. invoking enable_irq_wake() with a GPIO IRQ as in the following code to enable OTG wakeup is by no means portable and intuitive, and it is valid _only_ when GPIO35 is configured as USB_P2_1: enable_irq_wake( gpio_to_irq(35) ); To make things worse, not every GPIO is able to wakeup the system. Only a small number of them can, on either rising or falling edge, or when level is high (for keypad GPIOs). Thus, another new bit is introduced to indicate that the GPIO will wakeup the system: - MFP_LPM_WAKEUP_ENABLE The following macros can be used in platform code, and be OR'ed to the GPIO configuration to enable its wakeup: - WAKEUP_ON_EDGE_{RISE, FALL, BOTH} - WAKEUP_ON_LEVEL_HIGH The WAKEUP_ON_LEVEL_HIGH is used for keypad GPIOs _only_, there is no edge settings for those GPIOs. These WAKEUP_ON_* flags OR'ed on wrong GPIOs will be ignored in case that platform code author is careless enough. The tradeoff here is that the wakeup source is fully determined by the platform configuration, instead of enable_irq_wake(). Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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