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* ARM: dove: fix __io() definition to use bus based offsetEric Miao2010-09-191-3/+3
| | | | | | Signed-off-by: Eric Miao <eric.miao@canonical.com> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Dove: platform device registration for the sdio interfacesSaeed Bishara2010-07-163-0/+65
| | | | | Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* Merge branch 'origin' into devel-stableRussell King2010-03-082-2/+2
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-mx2/devices.c arch/arm/mach-mx2/devices.h sound/soc/pxa/pxa-ssp.c
| * Merge branch 'misc2' into develRussell King2010-02-251-1/+1
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| | * ARM: 5928/1: Change type of VMALLOC_END to unsigned long.Fenkart/Bostandzhyan2010-02-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Makes it consistent with VMALLOC_START Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5910/1: ARM: Add tmp register for addruart and loadspTony Lindgren2010-02-121-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise more complicated uart configuration won't be possible. We can use r1 for tmp register for both head.S and debug.S. NOTE: This patch depends on another patch to add the the tmp register into all debug-macro.S files. That can be done with: $ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/" arch/arm/*/include/*/debug-macro.S Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | mach-dove/common.c: remove unnecessary (void *) castsH Hartley Sweeten2010-02-051-4/+4
|/ | | | | | | | The (void *) cast is not needed when setting dev.platform_data to the address of the data. Remove the casts. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* ARM: Add Tauros2 L2 cache controller supportLennert Buytenhek2009-11-271-0/+4
| | | | | | | | | Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* ARM: add base support for Marvell Dove SoCSaeed Bishara2009-11-2723-0/+2103
The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
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