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| | * | | | | | | | | ARM: dts: dove: Rename "sa-sram" node to "sram"Krzysztof Kozlowski2019-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device node name should reflect generic class of a device so rename the "sa-sram" node to "sram". This will be also in sync with upcoming DT schema. No functional change. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
| | * | | | | | | | | ARM: dts: kirkwood: synology: Fix rs5c372 RTC entryWalter Schweizer2019-10-081-1/+1
| | | |_|/ / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the rtc-rs5c372.c driver the compatible entry has been renamed from rs5c372 to rs5c372a. Most dts files have been adapted. This patch completes the change. Signed-off-by: Walter Schweizer <ws.kernel@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
| * | | | | | | | | Merge tag 'tegra-for-5.5-arm-dt' of ↵Olof Johansson2019-11-0315-1653/+8910
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt ARM: tegra: Device tree changes for v5.5-rc1 Adds support for CPU frequency scaling on Tegra20 and Tegra30, EMC frequency scaling on Tegra30, SMMU support for VDE on Tegra30, the STMPE ADC found on Toradex T30 modules as well as fixes for eDP support on Venice2. * tag 'tegra-for-5.5-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: cardhu-a04: Add CPU Operating Performance Points ARM: tegra: cardhu-a04: Set up voltage regulators for DVFS ARM: tegra: trimslice: Add CPU Operating Performance Points ARM: tegra: paz00: Add CPU Operating Performance Points ARM: tegra: paz00: Set up voltage regulators for DVFS ARM: tegra: Add CPU Operating Performance Points for Tegra30 ARM: tegra: Add CPU Operating Performance Points for Tegra20 ARM: tegra: Add Tegra30 CPU clock ARM: tegra: Add Tegra20 CPU clock ARM: tegra: Add External Memory Controller node on Tegra30 ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6 ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30 ARM: tegra: Add eDP power supplies on Venice2 ARM: tegra: Add SOR0_OUT clock on Tegra124 ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules Link: https://lore.kernel.org/r/20191102144521.3863321-6-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | | ARM: tegra: cardhu-a04: Add CPU Operating Performance PointsDmitry Osipenko2019-10-291-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on Cardhu A04. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: cardhu-a04: Set up voltage regulators for DVFSDmitry Osipenko2019-10-291-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set minimum and maximum voltages, and couple CPU/CORE regulators. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: trimslice: Add CPU Operating Performance PointsDmitry Osipenko2019-10-291-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available now on TrimSlice. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: paz00: Add CPU Operating Performance PointsDmitry Osipenko2019-10-291-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Utilize common Tegra20 CPU OPP table. CPU DVFS is available now on AC100. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: paz00: Set up voltage regulators for DVFSDmitry Osipenko2019-10-291-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set minimum and maximum voltages, and couple CPU/CORE/RTC regulators. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add CPU Operating Performance Points for Tegra30Dmitry Osipenko2019-10-292-0/+2003
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Operating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary for them. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add CPU Operating Performance Points for Tegra20Dmitry Osipenko2019-10-292-0/+503
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Operating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary, like for example in a case of tegra20-trimslice which is outlet-powered device. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add Tegra30 CPU clockDmitry Osipenko2019-10-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All "geared" CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add Tegra20 CPU clockDmitry Osipenko2019-10-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add External Memory Controller node on Tegra30Dmitry Osipenko2019-10-291-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add External Memory Controller node to the device-tree. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: nyan-big: Add timings for RAM codes 4 and 6Dmitry Osipenko2019-10-291-1621/+6248
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add timings for RAM codes 4 and 6 and a timing for 528mHz of RAM code 1, which was missed due to the clock driver bug that is fixed now in all of stable kernels. Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Connect SMMU with Video Decoder Engine on Tegra30Dmitry Osipenko2019-10-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable IOMMU support for the video decoder. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add eDP power supplies on Venice2Thierry Reding2019-10-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power supplies needed to drive eDP on Venice2 were never hooked up, so things only worked because those regulators are already enabled by other devices. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add SOR0_OUT clock on Tegra124Thierry Reding2019-10-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is needed for eDP to properly function, so add it to the SOR device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | | | | | | | ARM: tegra: Add stmpe-adc DT node to Toradex T30 modulesPhilippe Schenker2019-10-293-24/+42
| | |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the stmpe-adc DT node as found on Toradex T30 modules Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | | | | | | | Merge tag 'sunxi-dt-for-5.5-1' of ↵Olof Johansson2019-11-039-1/+235
| |\ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual bunch of DT patches, with this time mostly: - Mali GPU support for the H6 - Two new crypto drivers enablement - A few fixes to our DTs, fixed through the validation effort - New boards: NanoPi Duo2 * tag 'sunxi-dt-for-5.5-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (22 commits) dt-bindings: arm: sunxi: add FriendlyARM NanoPi Duo2 ARM: dts: sun8i: add FriendlyARM NanoPi Duo2 arm64: allwinner: h6: Enable GPU node for Tanix TX6 arm64: dts: allwinner: bluetooth for Emlid Neutis N5 ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pins ARM: dts: sun9i: a80: Add Security System node ARM: dts: sun8i: a83t: Add Security System node arm64: dts: allwinner: sun50i: Add Crypto Engine node on H6 arm64: dts: allwinner: sun50i: Add crypto engine node on H5 arm64: dts: allwinner: sun50i: Add Crypto Engine node on A64 ARM: dts: sun8i: H3: Add Crypto Engine node ARM: dts: sun8i: R40: add crypto engine node dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine arm64: dts: allwinner: Add mali GPU supply for H6 boards arm64: dts: allwinner: Add ARM Mali GPU node for H6 ARM: dts: sun8i: a83t: a711: Add touchscreen node ARM: dts: sun5i: olinuxino micro: Fix AT24 node name ARM: dts: sun9i: Add missing watchdog clocks arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3 arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth ... Link: https://lore.kernel.org/r/1bf18c83-f41d-4353-9ca2-9585b8693df2.lettre@localhost Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | ARM: dts: sun8i: add FriendlyARM NanoPi Duo2Karl Palsson2019-11-022-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an Allwinner H3 based board, with 512MB ram, a USB OTG port, microsd slot, an onboard AP6212A wifi/bluetooth module, and a CSI connector. Full details and schematic available from vendor: http://wiki.friendlyarm.com/wiki/index.php/NanoPi_Duo2 Signed-off-by: Karl Palsson <karlp@tweak.net.au> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | ARM: dts: sunxi: h3/h5: add missing uart2 rts/cts pinsKarl Palsson2019-11-011-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | uart1 and uart3 had existing pin definitions for the rts/cts pairs. Add definitions for uart2 as well. Signed-off-by: Karl Palsson <karlp@tweak.net.au> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | ARM: dts: sun9i: a80: Add Security System nodeCorentin Labbe2019-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A80 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | ARM: dts: sun8i: a83t: Add Security System nodeCorentin Labbe2019-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG/RSA algorithms. It could be found on Allwinner SoC A80 and A83T This patch adds it on the Allwinner A83T SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | ARM: dts: sun8i: H3: Add Crypto Engine nodeCorentin Labbe2019-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Crypto Engine is a hardware cryptographic accelerator that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | ARM: dts: sun8i: R40: add crypto engine nodeCorentin Labbe2019-11-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Crypto Engine is a hardware cryptographic offloader that supports many algorithms. It could be found on most Allwinner SoCs. This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
| | * | | | | | | | ARM: dts: sun8i: a83t: a711: Add touchscreen nodeMylène Josserand2019-10-311-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable a FocalTech EDT-FT5x06 Polytouch touchscreen. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Signed-off-by: Maxime Ripard <mripard@kernel.org>
| | * | | | | | | | ARM: dts: sun5i: olinuxino micro: Fix AT24 node nameMaxime Ripard2019-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The node name in a device tree is supposed to be the class of the device, not its model (even if it's a pretty generic one). This was reported by the DT validation tools. Signed-off-by: Maxime Ripard <mripard@kernel.org>
| | * | | | | | | | ARM: dts: sun9i: Add missing watchdog clocksMaxime Ripard2019-10-211-0/+2
| | |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The watchdog has a clock, but it wasn't always listed. Add it to the devicetree where it's missing. Signed-off-by: Maxime Ripard <mripard@kernel.org>
| * | | | | | | | ARM: dts: atlas7: Fix "debounce-interval" property misspellingGeert Uytterhoeven2019-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "debounce_interval" was never supported. Link: https://lore.kernel.org/r/20191101160356.32034-3-geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Barry Song <baohua@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | Merge tag 'omap-for-v5.5/prm-signed' of ↵Olof Johansson2019-11-036-1/+156
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt PRM reset control dts changes for v5.5 merge window This series of changes adds the PRM reset driver nodes for am3/4, omap4/5 and dra7 SoCs. The reset driver changes make it easier to add support for various accelerators for TI SoCs in a more generic way. Note that this branch is based on the PRM reset driver changes branch. * tag 'omap-for-v5.5/prm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap5: Add PRM data ARM: dts: am43xx: Add PRM data ARM: dts: am33xx: Add PRM data ARM: dts: omap4: add PRM nodes ARM: dts: dra7: add PRM nodes soc: ti: omap-prm: add omap5 PRM data soc: ti: omap-prm: add am4 PRM data soc: ti: omap-prm: add dra7 PRM data soc: ti: omap-prm: add data for am33xx soc: ti: omap-prm: add omap4 PRM data soc: ti: omap-prm: add support for denying idle for reset clockdomain soc: ti: omap-prm: poll for reset complete during de-assert soc: ti: add initial PRM driver with reset control support dt-bindings: omap: add new binding for PRM instances Link: https://lore.kernel.org/r/pull-1572623173-281197@atomide.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | ARM: dts: omap5: Add PRM dataTero Kristo2019-10-101-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PRM data for OMAP54xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | | | | | | ARM: dts: am43xx: Add PRM dataTero Kristo2019-10-101-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PRM data for AM43xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | | | | | | ARM: dts: am33xx: Add PRM dataTero Kristo2019-10-101-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PRM data for AM33xx SoC. Initially this is used to provide reset support, but will be expanded later to support also powerdomain control. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | | | | | | ARM: dts: omap4: add PRM nodesTero Kristo2019-10-102-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PRM nodes for omap4 series of SoCs. These are initially used to support reset control for some of the nodes, but will be extended later to add powerdomain control and support for PRCM irqs among other things. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | | | | | | ARM: dts: dra7: add PRM nodesTero Kristo2019-10-101-0/+51
| | |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PRM nodes for dra7 series of SoCs. These are initially used to support reset control for some of the nodes, but will be extended later to add powerdomain control and support for PRCM irqs among other things. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | | | | | ARM: dts: mmp3-dell-ariel: Add a serial point aliasLubomir Rintel2019-11-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure UART3, where the console is, is called ttyS2. That is consistent with the early console. Link: https://lore.kernel.org/r/20191031163455.1711872-5-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | ARM: dts: mmp3-dell-ariel: Add a name to /memory nodeLubomir Rintel2019-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ponted out by DTC: <stdout>: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name Link: https://lore.kernel.org/r/20191031163455.1711872-4-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | ARM: dts: mmp3: Fix /soc/watchdog node nameLubomir Rintel2019-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a typo there that rightfully upsets DTS: <stdout>: Warning (simple_bus_reg): /soc/watchdog@2c000620: simple-bus unit address format error, expected "e0000620" Link: https://lore.kernel.org/r/20191031163455.1711872-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | ARM: dts: mmp3: Add a name to /clocks nodeLubomir Rintel2019-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It should have one and DTC is indeed unhappy about its absence: <stdout>: Warning (unit_address_vs_reg): /soc/clocks: node has a reg or ranges property, but no unit name Link: https://lore.kernel.org/r/20191031163455.1711872-2-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | ARM: dts: Add RDA8810PL GPIO controllersManivannan Sadhasivam2019-11-031-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPIO controllers for RDA8810PL SoC. There are 4 GPIO controllers in this SoC with maximum of 32 gpios. Except GPIOC, all controllers are capable of generating edge/level interrupts from first 8 lines. Link: https://lore.kernel.org/r/20191030101154.6312-2-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | | | | | Merge branch 'for_5.5/keystone-dts' of ↵Olof Johansson2019-11-035-6/+102
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/dt * 'for_5.5/keystone-dts' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: ARM: configs: keystone: enable cpts ARM: dts: k2l-netcp: add cpts refclk_mux node ARM: dts: k2hk-netcp: add cpts refclk_mux node ARM: dts: k2e-netcp: add cpts refclk_mux node ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/b ARM: dts: keystone-clocks: add input fixed clocks Link: https://lore.kernel.org/r/1572372856-20598-2-git-send-email-santosh.shilimkar@oracle.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | ARM: dts: k2l-netcp: add cpts refclk_mux nodeGrygorii Strashko2019-10-071-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KeyStone 66AK2L 1G Ethernet Switch Subsystems, can control an external multiplexer that selects one of up to 32 clocks for time sync reference (RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL register (offset: x08) in CPTS module and modelled as multiplexer clock. Hence, add cpts-refclk-mux clock node which allows to mux one of SYSCLK2, SYSCLK3, TIMI0, TIMI1, TSREFCLK clocks as CPTS reference clock [1] and group all CPTS properties under "cpts" subnode. [1] http://www.ti.com/lit/gpn/66ak2l06 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
| | * | | | | | | | ARM: dts: k2hk-netcp: add cpts refclk_mux nodeGrygorii Strashko2019-10-071-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KeyStone 66AK2H/K 1G Ethernet Switch Subsystems, can control an external multiplexer that selects one of up to 32 clocks for time sync reference (RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL register (offset: x08) in CPTS module and modelled as multiplexer clock. Hence, add cpts-refclk-mux clock node which allows to mux one of SYSCLK2, SYSCLK3, TIMI0, TIMI1, TSREFCLK clocks as CPTS reference clock [1] and group all CPTS properties under "cpts" subnode. [1] http://www.ti.com/lit/gpn/66ak2h14 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
| | * | | | | | | | ARM: dts: k2e-netcp: add cpts refclk_mux nodeGrygorii Strashko2019-10-071-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KeyStone 66AK2E 1G Ethernet Switch Subsystems, can control an external multiplexer that selects one of up to 32 clocks for time sync reference (RFTCLK) clock. This feature can be configured through CPTS_RFTCLK_SEL register (offset: x08) in CPTS module and modelled as multiplexer clock. Hence, add cpts-refclk-mux clock node which allows to mux one of SYSCLK2, SYSCLK3, TIMI0, TIMI1, TSIPCLKA, TSREFCLK, TSIPCLKB clocks as CPTS reference clock [1] and group all CPTS properties under "cpts" subnode. [1] http://www.ti.com/lit/gpn/66ak2e05 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
| | * | | | | | | | ARM: dts: k2e-clocks: add input ext. fixed clocks tsipclka/bGrygorii Strashko2019-10-071-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add set of fixed, external input clocks definitions for TSIPCLKA, TSIPCLKB clocks. Such clocks can be used as reference clocks for some HW modules (as cpts, for example) by configuring corresponding clock muxes. For these clocks real frequencies have to be defined in board files. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
| | * | | | | | | | ARM: dts: keystone-clocks: add input fixed clocksGrygorii Strashko2019-10-071-0/+27
| | |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add set of fixed, external input clocks definitions for TIMI0, TIMI1, TSREFCLK clocks. Such clocks can be used as reference clocks for some HW modules (as cpts, for example) by configuring corresponding clock muxes. For these clocks real frequencies have to be defined in board files. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
| * | | | | | | | Merge tag 'socfpga_dts_updates_for_v5.5' of ↵Olof Johansson2019-11-021-1/+1
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.5 - Arria10 - modify QSPI read-delay property - Agilex - Add QSPI support - Enable USB and LEDs - Add service layer, fpga manager support - Stratix10 - Update QSPI reg address * tag 'socfpga_dts_updates_for_v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex: add service layer, fpga manager and fpga region arm64: agilex: enable USB and LEDs on agilex devkit arm64: dts: altera: update QSPI reg addresses for Stratix10 arm64: dts: agilex: add QSPI support for Intel Agilex ARM: dts: arria10: Modify QSPI read_delay for Arria10 Link: https://lore.kernel.org/r/20191029143737.24850-1-dinguyen@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | ARM: dts: arria10: Modify QSPI read_delay for Arria10Dinh Nguyen2019-10-141-1/+1
| | |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default read delay for Arria10 QSPI module should be 3 on the Arria10 devkit. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
| * | | | | | | | Merge tag 'stm32-dt-for-v5.5-1' of ↵Olof Johansson2019-10-2816-50/+171
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT updates for v5.5, round 1 Highlights: ---------- MPU part: -Add and enable ADC support on stm32mp157a-dk1 -Add DAC support on stm32mp157c-ed1 -Add and enable VREFBUF support on stm32mp157a-dk1 -Add focaltech touchscreen on stm32mp157c-dk2 -Add hdmi support on stm32mp157a-dk1 -Fix issues seen during YAML DT validation -Fix regulators issues for all MPU boards MCU part: -Fix issues seen during YAML DT validation * tag 'stm32-dt-for-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: remove useless dma-ranges property for stm32f469 ARM: dts: stm32: remove useless dma-ranges property for stm32f429 ARM: dts: stm32: disable active-discharge for vbus_otg on stm32mp157a-avenger96 ARM: dts: stm32: Fix active discharge usage on stm32mp157 ARM: dts: stm32: change default minimal buck1 value on stm32mp157 ARM: dts: stm32: add PWR regulators support on stm32mp157 ARM: dts: stm32: remove useless interrupt from dsi node for stm32f469 ARM: dts: stm32: add hdmi audio support to stm32mp157a-dk1 board ARM: dts: stm32: Add DAC support to stm32mp157c-ed1 ARM: dts: stm32: Add DAC pins used on stm32mp157c-ed1 ARM: dts: stm32: fix regulator-sd_switch node on stm32mp157c-ed1 board ARM: dts: stm32: remove usb phy-names entries on stm32mp157c-ev1 ARM: dts: stm32: fix joystick node on stm32f746 and stm32mp157c eval boards ARM: dts: stm32: fix memory nodes to match with DT validation tool ARM: dts: stm32: add focaltech touchscreen on stm32mp157c-dk2 board ARM: dts: stm32: enable ADC support on stm32mp157a-dk1 ARM: dts: stm32: add ADC pins used on stm32mp157a-dk1 ARM: dts: stm32: Enable VREFBUF on stm32mp157a-dk1 ARM: dts: stm32: move ltdc pinctrl on stm32mp157a dk1 board Link: https://lore.kernel.org/r/02c39510-f36d-abbb-c76f-49aff07c0a08@st.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | | | | | ARM: dts: stm32: remove useless dma-ranges property for stm32f469Benjamin Gaignard2019-10-251-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove dma-ranges from ltdc node since it is already set on bus node. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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