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* ARM: sun6i: dt: Fix interrupt trigger typesMaxime Ripard2013-12-111-12/+15
| | | | | | | | | | | | | The Allwinner A31 uses the ARM GIC as its internal interrupts controller. The GIC can work on several interrupt triggers, and the A31 was actually setting it up to use a rising edge as a trigger, while it was actually a level high trigger, leading to some interrupts that would be completely ignored if the edge was missed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Cc: stable@vger.kernel.org # 3.12+ Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: sun6i: Fix the APB2 clock gates register sizeMaxime Ripard2013-10-051-1/+1
| | | | | | | The APB2 clocks gates are only a 32 bits register wide, and not 2 as set currently in the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun6i: Enable clock support in the DTSIMaxime Ripard2013-08-261-10/+134
| | | | | | | Now that the clock driver has support for the A31 clocks, we can add them to the DTSI and start using them in the relevant hardware blocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun6i: Add UART0 muxing optionsMaxime Ripard2013-08-221-0/+7
| | | | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Add PIO controller to A31 DTSIMaxime Ripard2013-08-221-0/+12
| | | | | | | | The A31 has a different set of pins than the one found on the A10 and A13. Now that we have support for the A31 pin set in the pinctrl driver, we can enable it in the DTSI with its own compatible. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Add Allwinner A31 DTSIMaxime Ripard2013-08-161-0/+156
The Allwinner A31 SoC is a multimedia SoC powered by 4 Cortex-A7 and a PowerVR GPU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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