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* ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock ratesSuman Anna2017-06-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers H11 & H12 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP_NOM values as defined in the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA Preferred Settings". The recommended maximum DPLL locked frequency is 2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. The value 465.92 MHz is used instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider value can be calculated. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: dts: omap5: fix clock node definitions to avoid build warningsTero Kristo2016-04-111-130/+130
| | | | | | | | | | | | Upcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for OMAP5 clock nodes: Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: dts: OMAP5: Fix the bypass clock source for dpll_iva and othersRavikumar Kattekola2015-03-061-4/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes 85dc74e9 (ARM: dts: omap5 clock data) On OMAP54xx, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock. But the bypass input is not directly routed to bypass clkout instead both CLKINP and CLKINPULOW are connected to bypass clkout via a mux. This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL and it's POR value is zero which selects the CLKINP as bypass clkout. which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck Fix this by adding another mux clock as parent in bypass mode. This design is common to most of the PLLs and the rest have only one bypass clock. Below is a list of the DPLLs that need this fix: DPLL_IVA, DPLL_PER, DPLL_USB and DPLL_CORE Signed-off-by: Ravikumar Kattekola <rk@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock ratesTero Kristo2014-08-261-6/+10
| | | | | | | | | | Similarly to DRA7, OMAP5 has l3 and l4 clock rates incorrectly calculated. Fixed by using proper divider clock types for the clock nodes. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Tested-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into ↵Mike Turquette2014-06-101-1/+1
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| * ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with ↵Nishanth Menon2014-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | higher frequencies OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle Correction(DCC) to operate safely at frequencies >= 1.4GHz. Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides this support. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | ARM: dts: omap5-clocks.dtsi: add ti, set-rate-parent to dss_dss_clkTomi Valkeinen2014-05-231-0/+1
| | | | | | | | | | | | | | | | Add ti,set-rate-parent to dss_dss_clk so that the DSS driver can set the rate. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | ARM: dts: omap54xx-clocks: Correct abe_iclk clock nodePeter Ujfalusi2014-05-231-4/+5
| | | | | | | | | | | | | | | | | | | | | | abe_iclk's parent is aess_fclk and not abe_clk. Also correct the parameters for clock rate calculation as used for OMAP4 since in PRCM level there's no difference between the two platform regarding to AESS/ABE clocking. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | ARM: dts: omap54xx-clocks: remove the autoidle properties for clock nodesPeter Ujfalusi2014-05-231-48/+0
|/ | | | | | | | | | In OMAP5 bit 8 in PRCM registers are not defined (Reserved) unlike their counterpart in OMAP4. It is better to not write to these bits. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* ARM: dts: omap5 clock dataTero Kristo2014-01-171-0/+1399
This patch creates a unique node for each clock in the OMAP5 power, reset and clock manager (PRCM). Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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