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Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This patch adds the basic machine file for the MesonX SoCs. Only Meson6
is populated.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add the UART definitions needed to support earlyprintk for MesonX SoCs
on UARTAO.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Export handle_fasteoi_irq to be able to use it in e.g. the Zynq gpio driver
since commit 6dd859508336 ("gpio: zynq: Fix IRQ handlers").
This fixes the following link issue:
ERROR: "handle_fasteoi_irq" [drivers/gpio/gpio-zynq.ko] undefined!
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Vincent Stehle <vincent.stehle@laposte.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Link: http://lkml.kernel.org/r/1408663880-29179-1-git-send-email-vincent.stehle@laposte.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: SoC updates for 3.18" from Shawn Guo:
The i.MX SoC updates for 3.18:
- Add initial devicetree support for i.MX1
- Support GPT per clock source from OSC for i.MX6
- A couple of parent selection corrections for i.MX6SL clock driver
- Support more chip revision for i.MX6
- Convert pr_warning to pr_warn
- Add exclusive gate clock support
- Add BYPASS support for i.MX6 PLL clocks
- Update i.MX6 clock tree for audio use case
- A couple of VF610 clock driver updates
* tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (30 commits)
ARM: imx_v6_v7_defconfig updates
ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM
arm: mach-imx: Convert pr_warning to pr_warn
ARM: imx: source gpt per clk from OSC for system timer
ARM: imx: add gpt_3m clk for i.mx6qdl
ARM: imx: fix register offset of pll7_usb_host gate clock
ARM: clk-imx6sl: refine clock tree for SSI
ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver
ARM: imx6sx: add BYPASS support for PLL clocks
ARM: imx6sl: add BYPASS support for PLL clocks
ARM: imx6q: add BYPASS support for PLL clocks
ARM: imx: add an exclusive gate clock type
ARM: clk-imx6q: refine clock tree for SSI
ARM: clk-imx6q: refine clock tree for ASRC
ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
ARM: clk-imx6q: refine clock tree for ESAI
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
ARM: clk-imx6sl: Remove csi_lcdif_sels[]
ARM: imx: clk-vf610: Add USBPHY clocks
ARM: imx: add cpufreq support for i.mx6sx
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by
default.
The fsl sai driver is used by the vf610-twr board, so let's enable it by
default.
simple-audio-card driver is used by the vf610-twr board, so let's enable it by
default.
Generated this patch by doing:
- make imx_v6_v7_defconfig
- make menuconfig and manually select options
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The imx weim driver is used by some mx27/mx1 boards, so let's enable it by
default.
Generated this patch by doing:
- make imx_v4_v5_defconfig
- make menuconfig and manually select CONFIG_IMX_WEIM
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v4_v5_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Use the more common pr_warn.
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.
There are some difference on this implementation of
gpt per clock source, see below for details:
i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock
of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC
for gpt per clk, and we must enable GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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There is a copy&paste error on register offset of pll7_usb_host gate
clock introduced by i.MX6 PLL bypass support patches. The error breaks
the ENET function, because it overwrites the pll6_enet gate bit.
Correct the offset for all i.MX6 clock drivers.
Thanks to Fugang Duan <B38611@freescale.com> for spotting the error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sx.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The imx6q clock driver currently hard-codes all PLL clocks to source
from OSC24M without BYPASS support. The patch adds the missing lvds_in
clock which is mutually exclusive with lvds_gate, and implements BYPASS
and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary
Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits
are implemented as mux clocks, and ENABLE bit of PLL clocks is
implemented as a gate clock after BYPASS mux.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously.
This patches adds an exclusive gate clock type specifically for such
case. The clock driver will need to call imx_clk_gate_exclusive() to
register a gate clock with parameter exclusive_mask indicating the mask
of gate bits which are mutually exclusive to this gate clock.
Right now, it only handles the exclusive gate clocks which are defined
in a single hardware register, which is the case we're running into
today. But it can be extended to handle exclusive gate clocks defined
in different registers later if needed.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share
the same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename
'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'.
Make the clock for ESAI more clear and align them with imx6sx.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Currently csi_lcdif_sels[] is a shared array for the providing the possible
clock parents for csi and lcdif blocks.
This is not correct, as csi and lcdif do not share the same clock parents.
Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in
order to describe the parents correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This commit adds PLL7 which is required for USBPHY1. It also adds
the USB PHY and USB Controller clocks and the gates to enable them.
Acked-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Add cpufreq support for i.MX6SX, using common
i.MX6Q cpufreq driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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At the end of the boot process, the clock framework might disable
required main PLL's. So far, this was no issue since drivers
requested clocks, which are descended of the main PLL's (e.g.
pll1_pfd1, which provides the system clock).
To archive the full 500MHz system clock, DDR clock need to be a
descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The
bootloader sets up the clocks accordingly before making use of
DDR at all. However, in Linux, there is no driver using PLL2,
which lead to PLL2 being disabled by the clock framework.
With this patch, we make sure that the main system clock and the
DDR clock are initially enabled and are kept enabled.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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This patch adds basic devicetree support for i.MX1 based SoCs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Add more revision support for the new i.MX6DQ tape-out (TO1.5). This
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3
and TO1.4 are never revealed.
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18
* r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
* tag 'renesas-soc4-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
Signed-off-by: Olof Johansson <olof@lixom.net>
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The r8a7794 support is always compiled using ARCH_MULTIPLATFORM which
selects USE_OF. So #ifdef CONFIG_USE_OF is unnecessary.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Enable low-level debug for Mediatek mt6589 SoC on UART0.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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When compiling with "ARCH=arm" and "allmodconfig",
with commit: 9cdc99919a95e8b54c1998b65bb1bfdabd47d27b [2/7] ARM: hisi: enable MCPM implementation
we will get:
/tmp/cc6DjYjT.s: Assembler messages:
/tmp/cc6DjYjT.s:63: Error: selected processor does not support ARM mode `ubfx r1,r0,#8,#8'
/tmp/cc6DjYjT.s:761: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:762: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:769: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:775: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:776: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:795: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:801: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:802: Error: selected processor does not support ARM mode `dsb '
Fix platmcpm compilation when ARMv6 is selected.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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HIP04 was added out of order, but so was the previous HISI debug uart
support as well. Minor reshuffling of order.
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge "pull request for hisilicon hip04 soc and D01 board updates" from Wei Xu:
ARM: mach-hisi: Hisilicon hip04 soc and D01 board updates for 3.18
- Add the CONFIG_MCPM_QUAD_CLUSTER configuration to enlarge cluster number from 2 to 4
- Enable MCPM on HiP04 SoC
- Enable 16 cores on HiP04 SoC
- Add platform & Fabric controller devicetree binding document for HiP04 SoC
- Add hip04.dtsi & hip04-d01.dts for hip04 SoC platform and D01 board
- Enable HiP04 SoC in both hi3xxx_defconfig & multi_v7_defconfig
- Add the support of Hisilicon HiP04 debug uart
* tag 'D01-for-3.18' of git://github.com/hisilicon/linux-hisi:
ARM: debug: add HiP04 debug uart
ARM: config: enable hisilicon hip04
ARM: dts: add hip04 dts
document: dt: add the binding on HiP04
ARM: hisi: enable HiP04
ARM: hisi: enable MCPM implementation
ARM: mcpm: support 4 clusters
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add the support of Hisilicon HiP04 debug uart.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Enable CONFIG_ARCH_HIP04 in both hi3xxx_defconfig & multi_v7_defconfig.
Since CONFIG_ARM_LPAE is disabled by default, only 3GB memory could be
support by this defconfig. User should enable CONFIG_ARM_LPAE locally to
support 16GB memory on hip04 platform.
Since hip04 doesn't belong to hi3xxx series, rename hi3xxx_defconfig to
hisi_defconfig.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add hip04-d01.dts & hip04.dtsi for hip04 SoC platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add Hisilicon HiP04 SoC platform & Fabric controller.
Fabric controller could be used to configure snoop filter among multiple
clusters.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Support HiP04 SoC what supports 16 cores. And it relies on MCPM
framework.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM
framework to manage power on HiP04 SoC.
Changelog:
v20:
* Disable L2 prefetch when the whole cluster is down.
* Move disabling snoop filter into power_down() after L2 prefetch
disabled.
* Remove delay in wait_for_power_down() after L2 prefetch disabled.
* Add the sleep polling in wait_for_power_down() again since we
need to wait L2 when the cluster is down.
v19:
* Add comments on those delay hacks.
* Update on checking core enabled counts in wait_for_power_down().
v18:
* Fix to release resource in probe().
* Check whether cpu is already up in the process of making cpu down.
* Add udelay in power up/down sequence.
* Optimize on setting relocation entry.
* Optimize on polling status in wait_for_power_down().
* Add mcpm critical operations.
v17:
* Parse bootwrapper parameters in DTS file.
* Fix to use msleep() in spinlock region.
v16:
* Parse bootwrapper parameters in command line instead.
v13:
* Restore power down operation in MCPM.
* Fix disabling snoop filter issue in MCPM.
v12:
* Use wfi as power down state in MCPM.
* Remove wait_for_powerdown() in MCPM because wfi is used now.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Add the CONFIG_MCPM_QUAD_CLUSTER configuration to enlarge cluster number
from 2 to 4.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Merge "Second Round of Renesas ARM Based SoC Clk Updates for v3.18" from Simon Horman.
* Add r8a7740, sh73a0 SoCs to MSTP bindings
* tag 'renesas-clk2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
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Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
SoC related changes for omaps for v3.18 merge window:
- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options
Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.
* tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (514 commits)
ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
ARM: dts: OMAP3+: Add PRM interrupt
ARM: omap: Remove stray ARCH_HAS_OPP references
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
ARM: AM437x: use pdata quirks for pinctrl information
ARM: DRA7: use pdata quirks for pinctrl information
ARM: OMAP5: use pdata quirks for pinctrl information
ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
ARM: OMAP4+: PM: use only valid low power state for suspend
ARM: OMAP4+: PM: Make logic state programmable
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
...
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OMAP4, OMAP5 and DRA7 share a lot of common logic and data structures.
These have been enabled in the previous patches, however, this also
means that OMAP5 or DRA7 only builds also need to build OMAP4 logic.
Update to reuse OMAP4 logic.
This fixes the 'undefined reference to 'omap4_pm_init_early'' in
OMAP5 or DRA7 only builds.
Fixes: 6af16a1dac5465c ("ARM: DRA7: Add hook in SoC initcalls to enable pm initialization")
Fixes: 628ed4717000789 ("ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization")
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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OPP is now a normal kernel library selected by its users rather than a
feature that architectures need to enable so ARCH_HAS_OPP serves no
function any more - remove the selects.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: minor modifications]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/soc
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With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
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