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| * | PCI: hv: Avoid use of hv_pci_dev->pci_slot after freeing itDexuan Cui2019-08-121-1/+1
| |/ | | | | | | | | | | | | | | | | | | The slot must be removed before the pci_dev is removed, otherwise a panic can happen due to use-after-free. Fixes: 15becc2b56c6 ("PCI: hv: Add hv_pci_remove_slots() when we unload the driver") Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org
* | Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas2019-09-239-23/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Make kirin_dw_pcie_ops constant (Nishka Dasgupta) - Make DesignWare "num-lanes" property optional and remove from relevant DTs (Hou Zhiqiang) * remotes/lorenzo/pci/dwc: arm64: dts: fsl: Remove num-lanes property from PCIe nodes ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes PCI: dwc: Return directly when num-lanes is not found dt-bindings: PCI: designware: Remove the num-lanes from Required properties PCI: kirin: Make structure kirin_dw_pcie_ops constant
| * | arm64: dts: fsl: Remove num-lanes property from PCIe nodesHou Zhiqiang2019-08-225-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the num-lanes property to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word). The PCIe link training is completed automatically through the selected SerDes protocol - the link width set-up is updated by hardware after power on reset, so the num-lanes property is not needed for Layerscape PCIe. The current num-lanes property was added erroneously, which actually indicates the maximum lanes the PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. The link width set by SerDes protocol will be overridden by the num-lanes property, hence the subsequent re-training will fail when the assigned lanes do not match the value in the num-lanes property. Remove the property to fix the issue Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | ARM: dts: ls1021a: Remove num-lanes property from PCIe nodesHou Zhiqiang2019-08-221-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the num-lanes property to avoid the driver setting the link width. On FSL Layerscape SoCs, the number of lanes assigned to PCIe controller is not fixed, it is determined by the selected SerDes protocol in the RCW (Reset Configuration Word). The PCIe link training is completed automatically through the selected SerDes protocol - the link width set-up is updated by hardware after power on reset, so the num-lanes property is not needed for Layerscape PCIe. The current num-lanes property was added erroneously, which actually indicates the maximum lanes the PCIe controller can support up to, instead of the lanes assigned to the PCIe controller. The link width set by SerDes protocol will be overridden by the num-lanes property, hence the subsequent re-training will fail when the assigned lanes do not match the value in the num-lanes property. Remove the property to fix the issue. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | PCI: dwc: Return directly when num-lanes is not foundHou Zhiqiang2019-08-221-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The num-lanes is optional since it is not needed on some platforms that bring up the link in firmware. The link programming is based on the num-lanes properties (which is optional); if it is not present code must return instead of fiddling with the lanes value to print an error message. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | dt-bindings: PCI: designware: Remove the num-lanes from Required propertiesHou Zhiqiang2019-08-221-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The num-lanes is not a mandatory property, e.g. on FSL Layerscape SoCs, the PCIe link training is completed automatically based on the selected SerDes protocol, it does not need the num-lanes to set-up the link width. Currently it is both a Required and Optional property, let's remove it from the Required properties. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | PCI: kirin: Make structure kirin_dw_pcie_ops constantNishka Dasgupta2019-08-211-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Static variable kirin_dw_pcie_ops, of type dw_pcie_ops, is used only once, when it is assigned to the constant field ops of variable pci (having type dw_pcie) so kirin_dw_pcie_ops is never modified. Make it constant to protect it from unintended modification. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
* | Merge branch 'remotes/lorenzo/pci/al'Bjorn Helgaas2019-09-239-1/+495
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add driver for Amazon Annapurna Labs PCIe controller (Jonathan Chocron) - Disable MSI-X since Annapurna Labs advertises it, but it's broken (Jonathan Chocron) - Disable VPD since Annapurna Labs advertises it, but it's broken (Jonathan Chocron) - Add ACS quirk since Annapurna Labs doesn't support ACS but does provide some equivalent protections (Ali Saidi) * remotes/lorenzo/pci/al: PCI: dwc: Add validation that PCIe core is set to correct mode PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driver dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge binding PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root Port PCI: Add ACS quirk for Amazon Annapurna Labs root ports PCI: Add Amazon's Annapurna Labs vendor ID # Conflicts: # drivers/pci/quirks.c
| * | PCI: dwc: Add validation that PCIe core is set to correct modeJonathan Chocron2019-09-162-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some PCIe controllers can be set to either Host or EP according to some early boot FW. To make sure there is no discrepancy (e.g. FW configured the port to EP mode while the DT specifies it as a host bridge or vice versa), a check has been added for each mode. Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
| * | PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driverJonathan Chocron2019-09-162-0/+377
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is DT based and utilizes the DesignWare APIs. It allows using a smaller ECAM range for a larger bus range - usually an entire bus uses 1MB of address space, but the driver can use it for a larger number of buses. This is achieved by using a HW mechanism which allows changing the BUS part of the "final" outgoing config transaction. There are 2 HW regs, one which is basically a bitmask determining which bits to take from the AXI transaction itself and another which holds the complementary part programmed by the driver. All link initializations are handled by the boot FW. Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | dt-bindings: PCI: Add Amazon's Annapurna Labs PCIe host bridge bindingJonathan Chocron2019-09-162-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Document Amazon's Annapurna Labs PCIe host bridge. Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
| * | PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root PortJonathan Chocron2019-09-161-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Root Port (identified by [1c36:0031]) doesn't support MSI-X. On some platforms it is configured to not advertise the capability at all, while on others it (mistakenly) does. This causes a panic during initialization by the pcieport driver, since it tries to configure the MSI-X capability. Specifically, when trying to access the MSI-X table a "non-existing addr" exception occurs. Example stacktrace snippet: SError Interrupt on CPU2, code 0xbf000000 -- SError CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33 Hardware name: Annapurna Labs Alpine V3 EVP (DT) pstate: 80000005 (Nzcv daif -PAN -UAO) pc : __pci_enable_msix_range+0x4e4/0x608 lr : __pci_enable_msix_range+0x498/0x608 sp : ffffff80117db700 x29: ffffff80117db700 x28: 0000000000000001 x27: 0000000000000001 x26: 0000000000000000 x25: ffffffd3e9d8c0b0 x24: 0000000000000000 x23: 0000000000000000 x22: 0000000000000000 x21: 0000000000000001 x20: 0000000000000000 x19: ffffffd3e9d8c000 x18: ffffffffffffffff x17: 0000000000000000 x16: 0000000000000000 x15: ffffff80116496c8 x14: ffffffd3e9844503 x13: ffffffd3e9844502 x12: 0000000000000038 x11: ffffffffffffff00 x10: 0000000000000040 x9 : ffffff801165e270 x8 : ffffff801165e268 x7 : 0000000000000002 x6 : 00000000000000b2 x5 : ffffffd3e9d8c2c0 x4 : 0000000000000000 x3 : 0000000000000000 x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffffffd3e9844680 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33 Hardware name: Annapurna Labs Alpine V3 EVP (DT) Call trace: dump_backtrace+0x0/0x140 show_stack+0x14/0x20 dump_stack+0xa8/0xcc panic+0x140/0x334 nmi_panic+0x6c/0x70 arm64_serror_panic+0x74/0x88 __pte_error+0x0/0x28 el1_error+0x84/0xf8 __pci_enable_msix_range+0x4e4/0x608 pci_alloc_irq_vectors_affinity+0xdc/0x150 pcie_port_device_register+0x2b8/0x4e0 pcie_portdrv_probe+0x34/0xf0 Notice that this quirk also disables MSI (which may work, but hasn't been tested nor has a current use case), since currently there is no standard way to disable only MSI-X. Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
| * | PCI/VPD: Prevent VPD access for Amazon's Annapurna Labs Root PortJonathan Chocron2019-09-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amazon Annapurna Labs PCIe Root Port exposes the VPD capability, but there is no actual support for it. Trying to access the VPD (for example, as part of lspci -vv or when reading the vpd sysfs file), results in the following warning print: pcieport 0001:00:00.0: VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add ACS quirk for Amazon Annapurna Labs root portsAli Saidi2019-09-161-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amazon's Annapurna Labs root ports don't advertise an ACS capability, but they don't allow peer-to-peer transactions and do validate bus numbers through the SMMU. Additionally, it's not possible for one RP to pass traffic to another RP. Signed-off-by: Ali Saidi <alisaidi@amazon.com> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add Amazon's Annapurna Labs vendor IDJonathan Chocron2019-09-161-0/+2
| |/ | | | | | | | | | | | | | | | | Add Amazon's Annapurna Labs vendor ID to pci_ids.h. Signed-off-by: Jonathan Chocron <jonnyc@amazon.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/resource'Bjorn Helgaas2019-09-239-30/+20
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Convert pci_resource_to_user() to a weak function to remove HAVE_ARCH_PCI_RESOURCE_TO_USER #defines (Denis Efremov) - Use PCI_SRIOV_NUM_BARS for idiomatic loop structure (Denis Efremov) - Fix Resizable BAR size suspend/restore for 1MB BARs (Sumit Saxena) - Correct "pci=resource_alignment" example in documentation (Alexey Kardashevskiy) * pci/resource: PCI: Correct pci=resource_alignment parameter example PCI: Restore Resizable BAR size bits correctly for 1MB BARs PCI: Use PCI_SRIOV_NUM_BARS in loops instead of PCI_IOV_RESOURCE_END PCI: Convert pci_resource_to_user() to a weak function # Conflicts: # drivers/pci/pci.c
| * | PCI: Correct pci=resource_alignment parameter exampleAlexey Kardashevskiy2019-08-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "pci=resource_alignment" parameter is described as requiring an order (not a size) and the code in pci_specified_resource_alignment() expects an order. But the example wrongly shows a size. Convert the example to an order. Fixes: 8b078c603249 ("PCI: Update "pci=resource_alignment" documentation") Link: https://lore.kernel.org/r/20190606032557.107542-1-aik@ozlabs.ru Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Restore Resizable BAR size bits correctly for 1MB BARsSumit Saxena2019-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a Resizable BAR Control Register, bits 13:8 control the size of the BAR. The encoded values of these bits are as follows (see PCIe r5.0, sec 7.8.6.3): Value BAR size 0 1 MB (2^20 bytes) 1 2 MB (2^21 bytes) 2 4 MB (2^22 bytes) ... 43 8 EB (2^63 bytes) Previously we incorrectly set the BAR size bits for a 1 MB BAR to 0x1f instead of 0, so devices that support that size, e.g., new megaraid_sas and mpt3sas adapters, fail to initialize during resume from S3 sleep. Correctly calculate the BAR size bits for Resizable BAR control registers. Link: https://lore.kernel.org/r/20190725192552.24295-1-sumit.saxena@broadcom.com Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=203939 Fixes: d3252ace0bc6 ("PCI: Restore resized BAR state on resume") Signed-off-by: Sumit Saxena <sumit.saxena@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org # v4.19+
| * | PCI: Use PCI_SRIOV_NUM_BARS in loops instead of PCI_IOV_RESOURCE_ENDDenis Efremov2019-08-082-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writing loop conditions as "i < NUM" is a common C idiom; using "i <= END" is unusual and thus prone to errors. Change loops to use the former. Link: https://lore.kernel.org/r/20190806140715.19847-1-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
| * | PCI: Convert pci_resource_to_user() to a weak functionDenis Efremov2019-08-086-23/+12
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert pci_resource_to_user() to a weak function so the existing architecture-specific implementations will automatically override the generic one. This allows us to remove HAVE_ARCH_PCI_RESOURCE_TO_USER definitions and avoid the conditional compilation for this single function. Link: https://lore.kernel.org/r/20190729101401.28068-1-efremov@linux.com Link: https://lore.kernel.org/r/20190729101401.28068-2-efremov@linux.com Link: https://lore.kernel.org/r/20190729101401.28068-3-efremov@linux.com Link: https://lore.kernel.org/r/20190729101401.28068-4-efremov@linux.com Link: https://lore.kernel.org/r/20190729101401.28068-5-efremov@linux.com Link: https://lore.kernel.org/r/20190729101401.28068-6-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> [bhelgaas: squash into one commit] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Paul Burton <paul.burton@mips.com> # MIPS
* | Merge branch 'pci/pciehp'Bjorn Helgaas2019-09-235-80/+67
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Cleanup pciehp LED/indicator control with a new consolidated pciehp_set_indicators() interface that controls both Attention and Power Indicators (Denis Efremov) * pci/pciehp: PCI: pciehp: Refer to "Indicators" instead of "LEDs" in comments PCI: pciehp: Remove pciehp_green_led_{on,off,blink}() PCI: pciehp: Remove pciehp_set_attention_status() PCI: pciehp: Combine adjacent indicator updates PCI: pciehp: Add pciehp_set_indicators() to set both indicators
| * | PCI: pciehp: Refer to "Indicators" instead of "LEDs" in commentsBjorn Helgaas2019-09-052-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The PCIe spec doesn't mention "green LEDs" or "amber LEDs". Replace those terms with "Power Indicator" and "Attention Indicator" so the comments match the spec language. Comment changes only. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: pciehp: Remove pciehp_green_led_{on,off,blink}()Denis Efremov2019-09-053-43/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove pciehp_green_led_{on,off,blink}() and use pciehp_set_indicators() instead, since the code is mostly the same. [bhelgaas: drop set_power_indicator() wrapper to reduce the number of interfaces] Link: https://lore.kernel.org/r/20190903111021.1559-5-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
| * | PCI: pciehp: Remove pciehp_set_attention_status()Denis Efremov2019-09-054-28/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove pciehp_set_attention_status() and use pciehp_set_indicators() instead, since the code is mostly the same. Link: https://lore.kernel.org/r/20190903111021.1559-4-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
| * | PCI: pciehp: Combine adjacent indicator updatesDenis Efremov2019-09-052-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Combine adjacent updates of power and attention indicators into a single pciehp_set_indicators() call. This sends one command to the hotplug controller instead of two. Link: https://lore.kernel.org/r/20190903111021.1559-3-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Reviewed-by: Lukas Wunner <lukas@wunner.de>
| * | PCI: pciehp: Add pciehp_set_indicators() to set both indicatorsDenis Efremov2019-09-052-0/+39
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pciehp_set_indicators() to set power and attention indicators with a single register write. This is a minor optimization because we frequently set both indicators and this can do it with a single command. It also reduces the number of interfaces related to the indicators and makes them more discoverable because callers use the PCI_EXP_SLTCTL_ATTN_IND_* and PCI_EXP_SLTCTL_PWR_IND_* definitions directly. [bhelgaas: extend commit log, s/PCI_EXP_SLTCTL_.*_IND_NONE/INDICATOR_NOOP/ so they don't look like things defined by the spec, add function doc, mask commands to make it obvious we only send valid commands (pcie_do_write_cmd() does mask it, but requires more effort to verify)] Link: https://lore.kernel.org/r/20190903111021.1559-2-efremov@linux.com Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge branch 'pci/p2pdma'Bjorn Helgaas2019-09-235-119/+300
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move P2PCMA PCI bus offset from generic dev_pagemap to pci_p2pdma_pagemap (Logan Gunthorpe) - Add provider's pci_dev to pci_p2pdma_pagemap (Logan Gunthorpe) - Apply host bridge whitelist for ACS (Logan Gunthorpe) - Whitelist some Intel host bridges for P2PDMA (Logan Gunthorpe) - Add attrs to pci_p2pdma_map_sg() to match dma_map_sg() (Logan Gunthorpe) - Add pci_p2pdma_unmap_sg() (Logan Gunthorpe) - Store P2PDMA mapping method in xarray (Logan Gunthorpe) - Map requests that traverse a host bridge (Logan Gunthorpe) - Allow IOMMU for host bridge whitelist (Logan Gunthorpe) * pci/p2pdma: PCI/P2PDMA: Update pci_p2pdma_distance_many() documentation PCI/P2PDMA: Allow IOMMU for host bridge whitelist PCI/P2PDMA: dma_map() requests that traverse the host bridge PCI/P2PDMA: Store mapping method in an xarray PCI/P2PDMA: Factor out __pci_p2pdma_map_sg() PCI/P2PDMA: Introduce pci_p2pdma_unmap_sg() PCI/P2PDMA: Add attrs argument to pci_p2pdma_map_sg() PCI/P2PDMA: Whitelist some Intel host bridges PCI/P2PDMA: Factor out host_bridge_whitelist() PCI/P2PDMA: Apply host bridge whitelist for ACS PCI/P2PDMA: Factor out __upstream_bridge_distance() PCI/P2PDMA: Add constants for map type results to upstream_bridge_distance() PCI/P2PDMA: Add provider's pci_dev to pci_p2pdma_pagemap struct PCI/P2PDMA: Introduce private pagemap structure
| * | PCI/P2PDMA: Update pci_p2pdma_distance_many() documentationLogan Gunthorpe2019-08-161-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The comment describing pci_p2pdma_distance_many() still referred to the devices being behind the same root port. This no longer applies so reword the documentation. Link: https://lore.kernel.org/r/20190730163545.4915-15-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-15-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Allow IOMMU for host bridge whitelistLogan Gunthorpe2019-08-161-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we map the requests correctly we can remove the iommu_present() restriction. Link: https://lore.kernel.org/r/20190730163545.4915-14-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-14-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: dma_map() requests that traverse the host bridgeLogan Gunthorpe2019-08-161-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any requests that traverse the host bridge will need to be mapped into the IOMMU, so call dma_map_sg() inside pci_p2pdma_map_sg() when appropriate. Similarly, call dma_unmap_sg() inside pci_p2pdma_unmap_sg(). Link: https://lore.kernel.org/r/20190730163545.4915-13-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-13-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Store mapping method in an xarrayLogan Gunthorpe2019-08-161-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When upstream_bridge_distance() is called, store the method required to map the DMA transfers in an xarray so it can be looked up efficiently on the hot path in pci_p2pdma_map_sg(). Link: https://lore.kernel.org/r/20190730163545.4915-12-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-12-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Factor out __pci_p2pdma_map_sg()Logan Gunthorpe2019-08-161-17/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Factor out the bus-only mapping into its own static function. No functional changes. The original pci_p2pdma_map_sg_attrs() will be used to decide whether this is an appropriate way to map. Link: https://lore.kernel.org/r/20190730163545.4915-11-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-11-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Introduce pci_p2pdma_unmap_sg()Logan Gunthorpe2019-08-164-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pci_p2pdma_unmap_sg() to the two places that call pci_p2pdma_map_sg(). This is a prep patch to introduce correct mappings for p2pdma transactions that go through the root complex. Link: https://lore.kernel.org/r/20190730163545.4915-10-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-10-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Add attrs argument to pci_p2pdma_map_sg()Logan Gunthorpe2019-08-163-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is to match the dma_map_sg() API which this function will have to call in an future patch. Add a pci_p2pdma_map_sg_attrs() function and helper to call it with no attributes just like the dma_map_sg() function. Link: https://lore.kernel.org/r/20190730163545.4915-9-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-9-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Whitelist some Intel host bridgesLogan Gunthorpe2019-08-161-4/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel devices do not have good support for P2P requests that span different host bridges as the transactions will cross the QPI/UPI bus and this does not perform well. Therefore, enable support for these devices only if the host bridges match. Add Intel devices that have been tested and are known to work. There are likely many others out there that will need to be tested and added. Link: https://lore.kernel.org/r/20190730163545.4915-8-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-8-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Factor out host_bridge_whitelist()Logan Gunthorpe2019-08-161-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Push both PCI devices into the whitelist checking function seeing some hardware will require us ensuring they are on the same host bridge. At the same time we rename root_complex_whitelist() to host_bridge_whitelist() to match the terminology used in the code. Link: https://lore.kernel.org/r/20190730163545.4915-7-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-7-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Apply host bridge whitelist for ACSLogan Gunthorpe2019-08-161-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a P2PDMA transfer is rejected due to ACS being set, we can also check the whitelist and allow the transactions. Do this by pushing the whitelist check into the upstream_bridge_distance() function. Link: https://lore.kernel.org/r/20190730163545.4915-6-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-6-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Factor out __upstream_bridge_distance()Logan Gunthorpe2019-08-161-40/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a prep patch to create a second level helper. There are no functional changes. The root complex whitelist code will be moved into this function in a subsequent patch. Link: https://lore.kernel.org/r/20190730163545.4915-5-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-5-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Add constants for map type results to upstream_bridge_distance()Logan Gunthorpe2019-08-161-37/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add constant flags to indicate how two devices will be mapped or if they are unsupported. upstream_bridge_distance() will now return the mapping type and the distance in a passed-by-reference argument. This helps annotate the code better, but the main reason is so we can use the information to store the required mapping method in an xarray. Link: https://lore.kernel.org/r/20190730163545.4915-4-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-4-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Add provider's pci_dev to pci_p2pdma_pagemap structLogan Gunthorpe2019-08-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The provider will be needed to figure out how to map a device. Link: https://lore.kernel.org/r/20190730163545.4915-3-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-3-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Introduce private pagemap structureLogan Gunthorpe2019-08-162-7/+20
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Move the PCI bus offset from the generic dev_pagemap structure to a specific pci_p2pdma_pagemap structure. This structure will grow in subsequent patches. Link: https://lore.kernel.org/r/20190730163545.4915-2-logang@deltatee.com Link: https://lore.kernel.org/r/20190812173048.9186-2-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
* | Merge branch 'pci/msi'Bjorn Helgaas2019-09-231-1/+1
|\ \ | | | | | | | | | | | | | | | | | | - Enable PCI_MSI_IRQ_DOMAIN support for RISC-V (Wesley Terpstra) * pci/msi: PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for RISC-V
| * | PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for RISC-VWesley Terpstra2019-08-081-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Add RISC-V as an arch that supports PCI_MSI_IRQ_DOMAIN. The related change to generate asm/msi.h is 251a44888183 ("riscv: include generic support for MSI irqdomains"). Link: https://lore.kernel.org/r/alpine.DEB.2.21.9999.1907251426450.32766@viisi.sifive.com Signed-off-by: Wesley Terpstra <wesley@sifive.com> [paul.walmsley@sifive.com: wrote patch description; split this patch from the arch/riscv patch] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'pci/misc'Bjorn Helgaas2019-09-239-251/+276
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use devm_add_action_or_reset() helper (Fuqian Huang) - Mark expected switch fall-through (Gustavo A. R. Silva) - Convert sysfs device attributes from __ATTR() to DEVICE_ATTR() (Kelsey Skunberg) - Convert sysfs file permissions from S_IRUSR etc to octal (Kelsey Skunberg) - Move SR-IOV sysfs functions to iov.c (Kelsey Skunberg) - Add pci_info_ratelimited() to ratelimit PCI messages separately (Krzysztof Wilczynski) - Fix "'static' not at beginning of declaration" warnings (Krzysztof Wilczynski) - Clean up resource_alignment parameter to not require static buffer (Logan Gunthorpe) - Add ACS quirk for iProc PAXB (Abhinav Ratna) - Add pci_irq_vector() and other stubs for !CONFIG_PCI (Herbert Xu) * pci/misc: PCI: Add pci_irq_vector() and other stubs when !CONFIG_PCI PCI: Add ACS quirk for iProc PAXB PCI: Force trailing new line to resource_alignment_param in sysfs PCI: Move pci_[get|set]_resource_alignment_param() into their callers PCI: Clean up resource_alignment parameter to not require static buffer PCI: Use static const struct, not const static struct PCI: Add pci_info_ratelimited() to ratelimit PCI separately PCI/IOV: Remove group write permission from sriov_numvfs, sriov_drivers_autoprobe PCI/IOV: Move sysfs SR-IOV functions to iov.c PCI: sysfs: Change permissions from symbolic to octal PCI: sysfs: Change DEVICE_ATTR() to DEVICE_ATTR_WO() PCI: sysfs: Define device attributes with DEVICE_ATTR*() PCI: Mark expected switch fall-through PCI: Use devm_add_action_or_reset()
| * | PCI: Add pci_irq_vector() and other stubs when !CONFIG_PCIHerbert Xu2019-09-211-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add stub functions pci_alloc_irq_vectors_affinity() and pci_irq_vector() when CONFIG_PCI is off so drivers can use them without resorting to ifdefs. Also move the PCI_IRQ_* macros outside of the ifdefs so they are always available. Fixes: 625f269a5a7a ("crypto: inside-secure - add support for PCI based FPGA development board") Link: https://lore.kernel.org/r/20190904122600.GA28660@gondor.apana.org.au Reported-by: kbuild test robot <lkp@intel.com> Reported-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Add ACS quirk for iProc PAXBAbhinav Ratna2019-09-051-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iProc PAXB Root Ports don't advertise an ACS capability, but they do not allow peer-to-peer transactions between Root Ports. Add an ACS quirk so each Root Port can be in a separate IOMMU group. [bhelgaas: commit log, comment, use common implementation style] Link: https://lore.kernel.org/r/1566275985-25670-1-git-send-email-srinath.mannam@broadcom.com Signed-off-by: Abhinav Ratna <abhinav.ratna@broadcom.com> Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Scott Branden <scott.branden@broadcom.com>
| * | PCI: Force trailing new line to resource_alignment_param in sysfsLogan Gunthorpe2019-09-051-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When 'pci=resource_alignment=' is specified on the command line, there is no trailing new line. Then, when it's read through the corresponding sysfs attribute, there will be no newline and a cat command will not show correctly in a shell. If the parameter is set through sysfs a new line will be stored and it will 'cat' correctly. To solve this, append a new line character in the show function if one does not already exist. Link: https://lore.kernel.org/r/20190822161013.5481-4-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Move pci_[get|set]_resource_alignment_param() into their callersLogan Gunthorpe2019-09-051-20/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both the functions pci_get_resource_alignment_param() and pci_set_resource_alignment_param() are now only called in one place: resource_alignment_show() and resource_alignment_store() respectively. There is no value in this extra set of functions so move both into their callers respectively. [bhelgaas: fold in "GFP_KERNEL while atomic" fix from Christoph Hellwig <hch@infradead.org> https://lore.kernel.org/r/20190902075006.GB754@infradead.org] Link: https://lore.kernel.org/r/20190822161013.5481-3-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Clean up resource_alignment parameter to not require static bufferLogan Gunthorpe2019-09-051-18/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the 'resource_alignment' parameter code to use kstrdup() in the initcall routine instead of a static buffer that wastes memory regardless of whether the feature is used. This allows us to drop 'COMMAND_LINE_SIZE' bytes (typically 256-4096 depending on architecture) of static data. This is similar to what has been done for the 'disable_acs_redir' parameter. Link: https://lore.kernel.org/r/20190822161013.5481-2-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | PCI: Use static const struct, not const static structKrzysztof Wilczynski2019-09-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the static keyword to the front of declarations of pci_regs_behavior[] and pcie_cap_regs_behavior[], which resolves compiler warnings when building with "W=1": drivers/pci/pci-bridge-emul.c:41:1: warning: ‘static’ is not at beginning of declaration [-Wold-style-declaration] const static struct pci_bridge_reg_behavior pci_regs_behavior[] = { ^ drivers/pci/pci-bridge-emul.c:176:1: warning: ‘static’ is not at beginning of declaration [-Wold-style-declaration] const static struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = { ^ Link: https://lore.kernel.org/r/20190826151436.4672-1-kw@linux.com Link: https://lore.kernel.org/r/20190828131733.5817-1-kw@linux.com Signed-off-by: Krzysztof Wilczynski <kw@linux.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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