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* Merge branch 'for_3.3/pm/omap4-mpuss' of ↵Tony Lindgren2011-12-0826-34/+2126
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap4
| * ARM: OMAP3: CPUidle: Make use of CPU PM notifiersSantosh Shilimkar2011-12-081-0/+15
| | | | | | | | | | | | | | | | | | | | Save VFP CPU context using CPU PM notifier chain. VFP context is lost when CPU hits OFF state. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: cpuidle: Switch to gptimer from twd in deeper C-states.Santosh Shilimkar2011-12-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU local timer(TWD) stops when the CPU is transitioning into deeper C-States. Since these timers are not wakeup capable, we need the wakeup capable global timer to program the wakeup time depending on the next timer expiry. It can be handled by registering a global wakeup capable timer along with local timers marked with (mis)feature flag CLOCK_EVT_FEAT_C3STOP. Then notify the clock events layer from idle code using CLOCK_EVT_NOTIFY_BROADCAST_ENTER/EXIT). ARM local timers are already marked with C3STOP feature. Add the notifiers to OMAP4 CPU idle code for the broadcast entry and exit. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add CPUidle supportSantosh Shilimkar2011-12-084-1/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add OMAP4 CPUIDLE support. CPU1 is left with defualt idle and the low power state for it is managed via cpu-hotplug. This patch adds MPUSS low power states in cpuidle. C1 - CPU0 ON + CPU1 ON + MPU ON C2 - CPU0 OFF + CPU1 OFF + MPU CSWR C3 - CPU0 OFF + CPU1 OFF + MPU OSWR OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more anymore just like CORE power domain. The deepest state supported is OSWr. Ofcourse when MPUSS and CORE PD transitions to OSWR along with device off mode, even the memory contemts are lost which is as good as the PD off state. On OMAP4 because of hardware constraints, no low power states are targeted when both CPUs are online and in SMP mode. The low power states are attempted only when secondary CPU gets offline to OFF through hotplug infrastructure. Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive C-state latency profiling. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: Fix errata i688 with MPU interconnect barriers.Santosh Shilimkar2011-12-087-1/+133
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4 SOC, intecronnects has many write buffers in the async bridges and they need to be drained before CPU enters into standby state. Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support but OMAP errata i688 (Async Bridge Corruption) needs to be taken care to avoid issues like system freeze, CPU deadlocks, random crashes with register accesses, synchronisation loss on initiators operating on both interconnect port simultaneously. As per the errata, if a data is stalled inside asynchronous bridge because of back pressure, it may be accepted multiple times, creating pointer misalignment that will corrupt next transfers on that data path until next reset of the system (No recovery procedure once the issue is hit, the path remains consistently broken). Async bridge can be found on path between MPU to EMIF and MPU to L3 interconnect. This situation can happen only when the idle is initiated by a Master Request Disconnection (which is trigged by software when executing WFI on CPU). The work-around for this errata needs all the initiators connected through async bridge must ensure that data path is properly drained before issuing WFI. This condition will be met if one Strongly ordered access is performed to the target right before executing the WFI. In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure that there is no synchronisation loss on initiators operating on both interconnect port simultaneously. Thanks to Russell for a tip to conver assembly function to C fuction there by reducing 40 odd lines of code from the patch. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add power domain statistics supportSantosh Shilimkar2011-12-081-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add MPUSS power domain OSWR supportSantosh Shilimkar2011-12-083-3/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS OSWR configuration is as below. - CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more anymore just like CORE power domain. The deepest state supported is OSWR. On OMAP4430 secure devices too, MPUSS off mode can't be used because of a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an independent state isn't supported on OMAP44XX devices. Ofcourse when MPUSS power domain transitions to OSWR along with device off mode, it eventually hits off state since memory contents are lost. Hence the MPUSS off mode independent state is not attempted without device off mode. All the necessary infrastructure code for MPUSS off mode is in place as part of this series. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add L2X0 cache lowpower supportSantosh Shilimkar2011-12-084-1/+144
| | | | | | | | | | | | | | | | | | | | | | | | When MPUSS hits off-mode, L2 cache is lost. This patch adds L2X0 necessary maintenance operations and context restoration in the low power code. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add WakeupGen and secure GIC low power supportSantosh Shilimkar2011-12-082-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add WakeupGen and secure GIC low power support to save and restore it's registers. WakeupGen Registers are saved to pre-defined SAR RAM layout and the restore is automatically done by hardware(ROM code) while coming out of MPUSS OSWR or Device off state. Secure GIC is saved using secure API and restored by hardware like WakeupGen. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: Remove un-used do_wfi() macro.Santosh Shilimkar2011-12-081-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | With OMAP4 suspend, idle and hotplug series, we no longer need do_wfi() macro. Remove the same. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: suspend: Add MPUSS power domain RETENTION supportSantosh Shilimkar2011-12-082-4/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MPUSS(MPU Sub System) power domain CSWR(Close Switch Retention) support to system wide suspend. For MPUSS power domain to hit retention(CSWR or OSWR), both CPU0 and CPU1 power domains need to be in OFF or DORMANT state, since CPU power domain CSWR is not supported by hardware Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Use custom omap_do_wfi() for default idle.Santosh Shilimkar2011-12-081-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Default arch_idle() isn't good enough for OMAP4 because of aync bridge errata and necessity of NOPs post WFI to avoid speculative prefetch aborts. Hence Use OMAP4 custom omap_do_wfi() hook for default idle. Later in the series, async bridge errata work-around patch updates the omap_do_wfi() with necessary interconnects barriers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: CPU1 wakeup workaround from Low power modesSantosh Shilimkar2011-12-081-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SGI(Software Generated Interrupts) are not wakeup capable from low power states. This is known limitation on OMAP4 and needs to be worked around by using software forced clockdomain wake-up. CPU0 forces the CPU1 clockdomain to software force wakeup. More details can be found in OMAP4430 TRM - Version J Section : 4.3.4.2 Power States of CPU0 and CPU1 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Program CPU1 to hit OFF when off-linedSantosh Shilimkar2011-12-084-5/+80
| | | | | | | | | | | | | | | | | | | | | | Program non-boot CPUs to hit lowest supported power state when it is off-lined using cpu hotplug framework. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: Remove __INIT from omap_secondary_startup() to re-use it for ↵Santosh Shilimkar2011-12-081-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hotplug. Remove the __INIT from omap_secondary_startup() so that it can be re-used for CPU hotplug. While at this, remove the un-used AUXBOOT register reference. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add CPUX OFF mode supportSantosh Shilimkar2011-12-088-2/+595
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the CPU0 and CPU1 off mode support. CPUX close switch retention (CSWR) is not supported by hardware design. The CPUx OFF mode isn't supported on OMAP4430 ES1.0 CPUx sleep code is common for hotplug, suspend and CPUilde. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add WakeupGen module as OMAP gic_arch_extnSantosh Shilimkar2011-12-084-1/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP WakeupGen is the interrupt controller extension used along with ARM GIC to wake the CPU out from low power states on external interrupts. The WakeupGen unit is responsible for generating the wakeup event from the incoming interrupts and enable bits. It is implemented in the MPU always ON power domain. During normal operation, WakeupGen delivers the external interrupts directly to the GIC. WakeupGen specification has one restriction as per Veyron version 1.6. It is SW responsibility to program interrupt enabling/disabling coherently in the GIC and in the WakeupGen enable registers. That is, a given interrupt for a given CPU is either enable at both GIC and WakeupGen, or disable at both, but no mix. That's the reason the WakeupGen is implemented as an extension of GIC. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP: PM: Add support to allocate the memory for secure RAMSantosh Shilimkar2011-12-084-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate the memory to save secure ram context which needs to be done when MPU is hitting OFF mode. The ROM code expects a physical address to this memory and hence use memblock APIs to reserve this memory as part of .reserve() callback. Maximum size as per secure RAM requirements is allocated. To keep omap1 build working, omap-secure.h file is created under plat-omap directory. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP: Add Secure HAL and monitor mode API infrastructure.Santosh Shilimkar2011-12-084-5/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP secure/emulation devices, certain APIs are exported by secure code. Add an infrastructure so that relevant operations on secure devices can be implemented using it. While at this, rename omap44xx-smc.S to omap-smc.S since the common APIs can be used on other OMAP's too. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Initialise all the clockdomains to supported statesSantosh Shilimkar2011-12-081-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | Initialise hardware supervised mode for all clockdomains if it's supported. Initiate sleep transition for other clockdomains, if they are not being used. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Avoid omap4_pm_init() on OMAP4430 ES1.0Santosh Shilimkar2011-12-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4430 ES1.0, Power Management features are not supported. Avoid omap4_pm_init() on ES1.0 silicon so that we can continue to use same kernel binary to boot on all OMAP4 silicons. The ES1.0 boot failure with OMAP4 PM series was because of the clockdomain initialisation code. Hardware supervised clockdomain mode isn't functional for all clockdomains on OMAP4430 ES1.0 silicon so avoid the same. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Kevin Hilman <khilman@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Keep static dep between MPUSS-EMIF and MPUSS-L3/L4 and DUCATI-L3Santosh Shilimkar2011-12-081-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per OMAP4430 TRM, the dynamic dependency between MPUSS -> EMIF and MPUSS -> L4PER/L3_* and DUCATI -> L3_* clockdomains is enable by default. Refer register CM_MPU_DYNAMICDEP description for details. But these dynamic dependencies doesn't work as expected. The hardware recommendation is to enable static dependencies for above clockdomains. Without this, system locks up or randomly crashes. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: PM: Add SAR RAM supportSantosh Shilimkar2011-12-084-0/+54
| | | | | | | | | | | | | | | | | | | | | | This patch adds SAR RAM support on OMAP4430. SAR RAM used to save and restore the HW context in low power modes. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: Export omap4_get_base*() rather than global address pointersSantosh Shilimkar2011-12-083-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch exports APIs to get base address for GIC distributor, CPU interface, SCU and PL310 L2 Cache which are used in OMAP4 PM code. This was suggested by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP4: Use WARN_ON() instead of BUG_ON() with graceful exitSantosh Shilimkar2011-12-081-1/+2
|/ | | | | | | | | | | | | | | | OMAP4 L2X0 initialisation code uses BUG_ON() for the ioremap() failure scenarios. Use WARN_ON() instead and allow graceful function exits. This was suggsted by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: 7194/1: OMAP: Fix build after a merge between v3.2-rc4 and ARM restart ↵Tony Lindgren2011-12-061-1/+2
| | | | | | | | | | | changes ARM restart changes needed changes to common.h to make it local. This conflicted with v3.2-rc4 DSS related hwmod changes that git mergetool was not able to handle. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7192/1: OMAP: Fix build error for omap1_defconfigTony Lindgren2011-12-061-0/+1
| | | | | | | | | | | Otherwise we get the following error: In function 'omap_init_consistent_dma_size': error: implicit declaration of function 'init_consistent_dma_size' Signed-off-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'vmalloc' of git://git.linaro.org/people/nico/linux into ↵Russell King2011-12-0596-1406/+179
|\ | | | | | | devel-stable
| * ARM: move VMALLOC_END down temporarily for shmobileNicolas Pitre2011-11-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | THIS IS A TEMPORARY HACK. The purpose of this is _only_ to avoid a regression on an existing machine while a better fix is implemented. On shmobile the consistent DMA memory area was set to 158MB in commit 28f0721a79 with no explanation. The documented size for this area should vary between 2MB and 14MB, and none of the other ARM targets exceed that. The included #warning is therefore meant to be noisy on purpose to get shmobile maintainers attention and this commit reverted once this consistent DMA size conflict is resolved. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Magnus Damm <damm@opensource.se> Cc: Paul Mundt <lethal@linux-sh.org>
| * ARM: big removal of now unused vmalloc.h filesNicolas Pitre2011-11-2659-866/+0
| | | | | | | | Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: add generic ioremap optimization by reusing static mappingsNicolas Pitre2011-11-263-25/+64
| | | | | | | | | | | | | | | | | | | | | | | | Now that we have all the static mappings from iotable_init() located in the vmalloc area, it is trivial to optimize ioremap by reusing those static mappings when the requested physical area fits in one of them, and so in a generic way for all platforms. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Kevin Hilman <khilman@ti.com> Tested-by: Jamie Iles <jamie@jamieiles.com>
| * ARM: simplify __iounmap() when dealing with section based mappingNicolas Pitre2011-11-261-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Firstly, there is no need to have a double pointer here as we're only walking the vmlist and not modifying it. Secondly, for the same reason, we don't need a write lock but only a read lock here, since the lock only protects the coherency of the list nothing else. Lastly, the reason for holding a lock is not what the comment says, so let's remove that misleading piece of information. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: move iotable mappings within the vmalloc regionNicolas Pitre2011-11-263-27/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to remove the build time variation between different SOCs with regards to VMALLOC_END, the iotable mappings are now allocated inside the vmalloc region. This allows for VMALLOC_END to be identical across all machines. The value for VMALLOC_END is now set to 0xff000000 which is right where the consistent DMA area starts. To accommodate all static mappings on machines with possible highmem usage, the default vmalloc area size is changed to 240 MB so that VMALLOC_START is no higher than 0xf0000000 by default. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Tested-by: Kevin Hilman <khilman@ti.com> Tested-by: Jamie Iles <jamie@jamieiles.com>
| * mm: add vm_area_add_early()Nicolas Pitre2011-11-182-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing vm_area_register_early() allows for early vmalloc space allocation. However upcoming cleanups in the ARM architecture require that some fixed locations in the vmalloc area be reserved also very early. The name "vm_area_register_early" would have been a good name for the reservation part without the allocation. Since it is already in use with different semantics, let's create vm_area_add_early() instead. Both vm_area_register_early() and vm_area_add_early() can be used together meaning that the former is now implemented using the later where it is ensured that no conflicting areas are added, but no attempt is made to make the allocation scheme in vm_area_register_early() more sophisticated. After all, you must know what you're doing when using those functions. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mm@kvack.org
| * ARM: move initialization of the high_memory variable earlierNicolas Pitre2011-11-183-2/+3
| | | | | | | | | | | | | | | | | | | | | | Some upcoming changes must know the VMALLOC_START value, which is based on high_memory, before bootmem_init() is called. The best location to set it is in sanity_check_meminfo() where the needed computation is already done, and in the non MMU case it is trivial to do now that the meminfo array is already sorted at that point. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: sort the meminfo array earlierNicolas Pitre2011-11-182-30/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | The meminfo array has to be sorted before sanity_check_meminfo() in arch/arm/mm/mmu.c is called for it to work properly. This also allows for a simpler find_limits() in arch/arm/mm/init.c. The sort is moved to arch/arm/kernel/setup.c because that's where the meminfo array is populated. Eventually this should be improved upon to make the memory bank parser a bit more robust against problems such as overlapping memory ranges. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: realview-eb11mp: fix map_desc alignmentRob Herring2011-11-181-2/+2
| | | | | | | | | | | | | | | | | | REALVIEW_EB11MP_GIC_CPU_BASE is not 4KB aligned which causes an overlapping mapping. Use REALVIEW_EB11MP_SCU_BASE instead which is aligned. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: realview: fix map_desc alignmentRob Herring2011-11-181-2/+2
| | | | | | | | | | | | | | | | | | REALVIEW_PBX_TILE_GIC_CPU_BASE is not 4KB aligned which causes an overlapping mapping. Use REALVIEW_PBX_TILE_SCU_BASE instead which is aligned. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: versatile: remove overlapping map_desc entryRob Herring2011-11-181-5/+0
| | | | | | | | | | | | | | | | The map_desc for VERSATILE_GPIO0_BASE overlaps with VERSATILE_SCTL_BASE. The overlapping entry can be removed. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: plat-iop: remove arch specific special handling for ioremapNicolas Pitre2011-11-184-75/+0
| | | | | | | | | | | | A generic version should replace this later. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: mach-ixp23xx: remove arch specific special handling for ioremapNicolas Pitre2011-11-181-29/+0
| | | | | | | | | | | | | | A generic version should replace this later. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Deepak Saxena <dsaxena@linaro.org>
| * ARM: mach-kirkwood: remove arch specific special handling for ioremapNicolas Pitre2011-11-181-25/+0
| | | | | | | | | | | | A generic version should replace this later. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: mach-orion5x: remove arch specific special handling for ioremapNicolas Pitre2011-11-181-25/+0
| | | | | | | | | | | | A generic version should replace this later. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: mach-bcmring: use proper constant to identify DMA memory areaNicolas Pitre2011-11-181-1/+1
| | | | | | | | | | | | | | Using VMALLOC_END implies a presumption about the layout which is best avoided, even if in practice this would not change much. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: plat-omap: remove arch specific special handling for ioremapNicolas Pitre2011-11-186-170/+8
| | | | | | | | | | | | | | | | | | | | A generic version should replace this later. As io.c has become nearly empty, omap_init_consistent_dma_size() is moved into common.c so that io.c can be removed entirely. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Kevin Hilman <khilman@ti.com>
| * ARM: mach-tegra: remove arch specific special handling for ioremapNicolas Pitre2011-11-162-27/+0
| | | | | | | | | | | | | | A generic version should replace this later. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com>
| * ARM: mach-davinci: remove arch specific special handling for ioremapNicolas Pitre2011-11-153-57/+1
| | | | | | | | | | | | A generic version should replace this later. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: mach-at91: remove arch specific special handling for ioremapNicolas Pitre2011-11-152-26/+0
| | | | | | | | | | | | A generic version should replace this later. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: plat-mxc: remove inclusion of <mach/vmalloc.h>Nicolas Pitre2011-11-151-2/+0
| | | | | | | | Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
| * ARM: mach-prima2: don't define SIRFSOC_VA in terms of VMALLOC_ENDNicolas Pitre2011-11-151-2/+4
| | | | | | | | | | | | | | ... since it is going to change. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Barry Song <baohua.song@csr.com>
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