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* powerpc: Fix a build problem on ppc32 with new DMA_ATTRsTakashi Iwai2008-07-151-1/+1
| | | | | | | The new dma_attrs support must only be enabled for 64 bits as it's not been implemented for 32 bits yet. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* ibm_newemac: Add MII mode support to the EMAC RGMII bridge.Grant Erickson2008-07-151-0/+6
| | | | | | | | | | | | | | | | This patch adds support to the RGMII handler in the EMAC driver for the MII PHY mode such that device tree entries of the form `phy-mode = "mii";' are recognized and handled appropriately. While logically, in software, "gmii" and "mii" modes are the same, they are wired differently, so it makes sense to allow DTS authors to specify each explicitly. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Don't spin on sync instruction at boot timeSonny Rao2008-07-151-1/+2
| | | | | | | | | | Push the sync below the secondary smp init hold loop and comment its purpose. This should speed up boot by reducing global traffic during the single-threaded portion of boot. Signed-off-by: Sonny Rao <sonnyrao@us.ibm.com> Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add VSX load/store alignment exception handlerMichael Neuling2008-07-151-1/+57
| | | | | | | | | | | VSX loads and stores will take an alignment exception when the address is not on a 4 byte boundary. This add support for these alignment exceptions and will emulate the requested load or store. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: fix giveup_vsx to save registers correctlyMichael Neuling2008-07-155-7/+16
| | | | | | | | | | | giveup_vsx didn't save the FPU and VMX regsiters. Change it to be like giveup_fpr/altivec which save these registers. Also update call sites where FPU and VMX are already saved to use the original giveup_vsx (renamed to __giveup_vsx). Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: support for latencytopArnd Bergmann2008-07-152-10/+30
| | | | | | | | Implement save_stack_trace_tsk on powerpc, so that we can run with latencytop. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Remove unnecessary condition when sanity-checking WIMG bitsDave Kleikamp2008-07-152-4/+3
| | | | | | | | | | | It is okay for both _PAGE_GUARDED and _PAGE_COHERENT (G and M) to be set in the same pte. In fact, even if that were not the case, there doesn't seem to be any place where G is set without also setting I (_PAGE_NO_CACHE), so the test for I is sufficient as a condition to clear _PAGE_COHERENT when filling the hash table. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add PPC_FEATURE_PSERIES_PERFMON_COMPATNathan Lynch2008-07-152-2/+7
| | | | | | | | | | | | | | | | | | | | | Background from Maynard Johnson: As of POWER6, a set of 32 common events is defined that must be supported on all future POWER processors. The main impetus for this compat set is the need to support partition migration, especially from processor P(n) to processor P(n+1), where performance software that's running in the new partition may not be knowledgeable about processor P(n+1). If a performance tool determines it does not support the physical processor, but is told (via the PPC_FEATURE_PSERIES_PERFMON_COMPAT bit) that the processor supports the notion of the PMU compat set, then the performance tool can surface just those events to the user of the tool. PPC_FEATURE_PSERIES_PERFMON_COMPAT indicates that the PMU supports at least this basic subset of events which is compatible across POWER processor lines. Signed-off-by: Nathan Lynch <ntl@pobox.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: Add driver for Barrier Synchronization RegisterSonny Rao2008-07-154-0/+322
| | | | | | | | | | | | Adds a character driver for BSR support on IBM POWER systems including Power5 and Power6. The BSR is an optional processor facility not currently implemented by any other processors. It's primary purpose is fast large SMP synchronization. More details on the BSR are in comments to the code which follows. This patch adds BSR driver to pseries_defconfig. Signed-off-by: Sonny Rao <sonnyrao@linux.vnet.ibm.com> Signed-off-by: Joel Schopp <jschopp@austin.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* powerpc: mman.h export fixupsStephen Rothwell2008-07-152-3/+6
| | | | | | | | | | | | | | | | | Commit ef3d3246a0d06be622867d21af25f997aeeb105f ("powerpc/mm: Add Strong Access Ordering support") in the powerpc/{next,master} tree caused the following in a powerpc allmodconfig build: usr/include/asm/mman.h requires linux/mm.h, which does not exist in exported headers We should not use CONFIG_PPC64 in an unprotected (by __KERNEL__) section of an exported include file and linux/mm.h is not exported. So protect the whole section that is CONFIG_PPC64 with __KERNEL__ and put the two introduced includes in there as well. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge commit 'gcl/gcl-next'Benjamin Herrenschmidt2008-07-1524-257/+1620
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| * powerpc: Modify MPC52xx maintainers entry to cover all MPC5xxx partsGrant Likely2008-07-121-3/+1
| | | | | | | | | | | | | | | | Linux now supports the MPC5121 part and is handled by the same maintainer. Update MAINTAINERS to reflect this. Also remove URLs which are out of date or are not particularly relevant. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5121: Add support for CPLD on MPC5121ADS boardJohn Rigby2008-07-125-1/+233
| | | | | | | | | | | | | | | | | | Add a interrupt host for the interrupt controller in the mpc5121ads cpld. PCI interrupts are 0-7 the rest are 8-15 Touchscreen pendown irq is hardwired to irq1 All other irqs are chained to irq0 Signed-off-by: John Rigby <jrigby@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5121: Add generic board support for MPC5121 platformsJohn Rigby2008-07-126-63/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move shared code from mpc5121_ads.c to new file mpc512x_shared.c - mpc512x_find_ips_freq -> unchanged - contents of mpc5121_ads_init_IRQ -> mpc512x_init_IRQ - looking for fsl,mpc5121-ipic instead of fsl,ipic - mpc5121_ads_declare_of_platform_devices -> mpc5121_declare_of_platform_devices - and use compatible for lookup instead of node name Add new generic board setup mpc5121_generic.c Signed-off-by: John Rigby <jrigby@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5121: Add clock driverJohn Rigby2008-07-124-0/+732
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Plugs into the generic powerpc clock driver in arch/powerpc/kernel/clock.c The following subset of clk_interface is implemented: clk_get, clk_put: get clock via name, release clock clk_enable, clk_disable: enable or disable clock clk_get_rate: get clock rate in Hz clk_set_rate: stubbed clk_round_rate: stubbed clk_set_parent: NULL clk_get_parent: NULL Signed-off-by: John Rigby <jrigby@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5121: Update device tree for MPC5121ADS evaluation boardJohn Rigby2008-07-121-11/+299
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current device tree is only bare bones. This patch adds nodes to make it a complete tree for the MPC5121ads. Added nodes include: mbx - opengl coprocessor nfc - nand flash controller cpld-pic - on board cpld rtc clock - clock control pmc - power management control gpio mscan - can module i2c axe - audio coprocessor display - display interface unit mdio ethernet usb ioctl - pin config pata ac97 - PSC configured as AC97 pscfifo - psc fifo configuration dma pci Fix typo in header changing MDS to ADS. Add a compatible property of the form "fsl,mpc5121-..." to nodes missing one. Changed localbus compatible to fsl,mpc5121-localbus, this does not break anything because the only code that uses it finds it via the node name, not compatible. Signed-off-by: John Rigby <jrigby@freescale.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5200: fix compile warnings in bestcomm driverGrant Likely2008-07-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for the following compiler warnings: CC arch/powerpc/sysdev/bestcomm/bestcomm.o arch/powerpc/sysdev/bestcomm/bestcomm.c: In function 'mpc52xx_bcom_probe': arch/powerpc/sysdev/bestcomm/bestcomm.c:446: warning: format '%08lx' expects type 'long unsigned int', but argument 2 has type 'phys_addr_t' CC arch/powerpc/sysdev/bestcomm/sram.o arch/powerpc/sysdev/bestcomm/sram.c: In function 'bcom_sram_init': arch/powerpc/sysdev/bestcomm/sram.c:89: warning: format '%08lx' expects type 'long unsigned int', but argument 3 has type 'phys_addr_t' Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5200: Add PSC helpers for bestcomm engineGrant Likely2008-07-122-0/+100
| | | | | | | | | | | | | | | | | | Simplify the interface for setting up bestcomm DMA to PSCs by adding some helper functions. The helper function sets the correct values for the initator and ipr values in PSC DMA tasks based on the PSC number. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5200_wdt: use linux/of_platform.h instead of asmStephen Rothwell2008-07-121-1/+1
| | | | | | | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc52xx_psc_spi: use linux/of_platform.h instead of asmStephen Rothwell2008-07-121-1/+1
| | | | | | | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/pata_mpc52xx: use linux/of_platform.h instead of asmStephen Rothwell2008-07-121-1/+1
| | | | | | | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5200: add missing MSCAN FDT nodes for TQM52xxWolfgang Grandegger2008-07-121-0/+14
| | | | | | | | | | | | | | | | This patch adds the still missing FDT nodes for the MSCAN devices for the TQM52xx modules. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * OpenFirmware: Include <linux/of_i2c.h> from of_i2c.c.Robert P. J. Day2008-07-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | drivers/of/of_i2c.c should include <linux/of_i2c.h> for the prototype for of_register_i2c_devices(). Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Acked-by: Jean Delvare <khali@linux-fr.org> Acked-by: Jochen Friedrich <jochen@scram.de> Acked-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/i2c: Convert i2c-mpc into an of_platform driverJon Smirl2008-07-122-177/+60
| | | | | | | | | | | | | | | | | | Convert i2c-mpc to an of_platform driver. Utilize the code in drivers/of-i2c.c to make i2c modules dynamically loadable by the device tree. Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * powerpc/mpc5200: PCI write combine timerAndre Schwarz2008-07-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On MPC5200 the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00 leads to _very poor_ performance as a PCI target since external burst won't be possible at all. Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | Merge commit 'jwb/jwb-next'Benjamin Herrenschmidt2008-07-1523-265/+2086
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| * | powerpc: Fix problems with 32bit PPC's running with >= 4GB of RAMStefan Roese2008-07-093-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables 32bit PPC's (with 36bit physical address space, e.g. IBM/AMCC PPC44x) to run with >= 4GB of RAM. Mostly its just replacing types (unsigned long -> phys_addr_t). Tested on an AMCC Katmai with 4GB of DDR2. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| * | powerpc/44x: Update ppc44x_defconfigJosh Boyer2008-07-091-45/+104
| | | | | | | | | | | | | | | | | | Add the virtex and sam440ep platforms to the multiboard defconfig Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| * | powerpc/44x: Support NAND boot for Rev A Warp boardsSean MacLennan2008-07-091-2/+7
| | | | | | | | | | | | | | | | | | | | | Allow the Rev A Warp boards to boot from NAND. Signed-off-by: Sean MacLennan <smaclennan@pikatech.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| * | powerpc: rework 4xx PTE access and TLB missBenjamin Herrenschmidt2008-07-095-207/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is some preliminary work to improve TLB management on SW loaded TLB powerpc platforms. This introduce support for non-atomic PTE operations in pgtable-ppc32.h and removes write back to the PTE from the TLB miss handlers. In addition, the DSI interrupt code no longer tries to fixup write permission, this is left to generic code, and _PAGE_HWWRITE is gone. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| * | Merge branch 'virtex-for-2.6.27' of ↵Josh Boyer2008-07-0913-3/+1787
| |\ \ | | |/ | |/| | | | git://git.secretlab.ca/git/linux-2.6-virtex into 4xx-next
| | * powerpc/440: Convert Virtex ML507 device tree to dts-v1Grant Likely2008-07-091-99/+157
| | | | | | | | | | | | Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| | * powerpc/bootwrapper: Allow user to specify additional default targetsGrant Likely2008-07-092-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is inconvenient to add additional default targets to the bootwrapper Makefile for each new board supported which just needs a different dts file. This change allows the defconfig to specify additional build targets. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| | * powerpc/bootwrapper: add missing bit of simpleImage targetGrant Likely2008-07-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | The wrapper script is missing the bits needed for building generic simpleImage targets (targets which don't depend on any particular firmware interface and retrieve all their data from the device tree). Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| | * powerpc/bootwrapper: Add documentation of boot wrapper targetsGrant Likely2008-07-042-1/+155
| | | | | | | | | | | | | | | | | | | | | | | | There have been many questions on and off the mailing list about how exactly the bootwrapper is used for embedded targets. Add some documentation and help text to try and clarify the system. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| | * powerpc/virtex: add defconfig for virtex 5 platformsJohn Linn2008-07-041-0/+1107
| | | | | | | | | | | | | | | | | | | | | This defconfig file is specific to Xilinx Virtex 5 FXT platform. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| | * powerpc/virtex: add Xilinx 440 cpu to the cputableJohn Linn2008-07-041-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Updates the cputable to include the 440 processor found in the Xilinx Virtex5 FXT FPGA. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| | * powerpc/virtex: add Xilinx Virtex 5 ppc440 platform supportJohn Linn2008-07-043-0/+87
| | | | | | | | | | | | | | | | | | | | | Support for the Xilinx Virtex5 FXT 440 is being added. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| | * powerpc/virtex: Fix booting of Xilinx FPGAs with 16550 for 405 and 440John Linn2008-07-044-2/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes add processing to initialize the Xilinx 16550 UART in the boot wrapper for Virtex targets without firmware. Normally the boot wrapper assumes that the serial port has already been initialized by firmware. The wrapper was also modified to add the 440 build. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| | * powerpc/virtex: add dts file for ML507 reference designJohn Linn2008-07-041-0/+238
| | | | | | | | | | | | | | | | | | | | | | | | This new file adds support for the ML507 reference design. The ML507 uses the Virtex 5 FXT FPGA which embeds a ppc440 core. Signed-off-by: John Linn <john.linn@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | | powerpc/fsl: update crypto node definition and device tree instancesKim Phillips2008-07-1427-143/+268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | delete obsolete device-type property, delete model property (use compatible property instead), prepend "fsl," to Freescale specific properties. Add nodes to device trees that are missing them, and fix broken property values in other trees. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/fsl: Refactor device bindingsKumar Gala2008-07-1427-1206/+1077
| | | | | | | | | | | | | | | | | | | | | Moved Freescale SoC related bindings out of booting-without-of.txt and into their own files. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/85xx: Minor fixes for 85xxds and 8536ds board.Jason Jin2008-07-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Remove the "uninitialized use" compile warning and avoid potential runtime issue. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc: Add 82xx/83xx/86xx to 6xx MultiplatformKumar Gala2008-07-144-44/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There isn't any reason at this point that we can't build 82xx, 83xx & 86xx support in with the other 6xx based boards. Twiddle the Kconfigs to allow this. This allows us to remove the machine type selection for related to 6xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/85xx: publish of device for cds platformsDave Jiang2008-07-141-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Publish the devices listed in dts under SOC as of_device for 85xx_cds platform. The devices are needed by the 85xx EDAC driver. Signed-off-by: Dave Jiang <djiang@mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/booke: don't reinitialize time baseKumar Gala2008-07-141-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason long ago I decided that we should zero out the time base when we calibrate the decrementer. The problem is that this can be harmful in SMP systems where the firmware has already synchronized the time bases on the various cores. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/86xx: Refactor pic initKumar Gala2008-07-146-111/+86
| | | | | | | | | | | | | | | | | | | | | Moved the pic initialization into its own common file and out of the board code. Also fixed the OF reference counting on the mpic node. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/CPM: Add i2c pins to dts and board setupJochen Friedrich2008-07-147-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize I2C pins on boards with CPM1/CPM2 controllers and document the i2c bus in booting-without-of. The boards don't have any I2C chips connected to the I2C bus, so unless some external chips are connected to the boards, this code is just an example of setting everything else up. Signed-off-by: Jochen Friedrich <jochen@scram.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | cpm_uart: Support uart_wait_until_sent()Laurent Pinchart2008-07-141-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set port->fifosize to the software FIFO size, and update the port timeout when the baud rate is modified. SCC ports have an optional 32 byte hardware FIFO which is currently not taken into account, as there is no documented way to check when the FIFO becomes empty. Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | powerpc/85xx: Add support for MPC8536DSKumar Gala2008-07-147-0/+2193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the MPC8536 process and MPC8536DS reference board. The MPC8536 is an e500v2 based SoC which eTSEC, USB, SATA, PCI, and PCIe. The USB and SATA IP blocks are similiar to those on the PQ2 Pro SoCs and thus use the same drivers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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