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| | * | ARM: exynos5420: create a DT header defining CLK IDsAndrzej Hajda2014-01-081-0/+188
| | * | clk: exynos5250: replace clock ID private enums with IDs from DT headerAndrzej Hajda2014-01-081-295/+264
| | * | ARM: exynos5250: create a DT header defining CLK IDsAndrzej Hajda2014-01-081-0/+159
| | * | clk: exynos4: replace clock ID private enums with IDs from DT headerAndrzej Hajda2014-01-081-455/+402
| | * | ARM: exynos4: create a DT header defining CLK IDsAndrzej Hajda2014-01-081-0/+244
| | * | clk: exynos5250: register APLL rate tableAndrew Bresticker2014-01-081-1/+24
| | * | clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apllSachin Kamat2013-12-301-1/+2
| | * | clk: samsung: exynos5250: Fix parents of gate clocks from MFC domainTomasz Figa2013-12-301-3/+5
| | * | clk: samsung: exynos5250: Correct parent list of audio muxesTomasz Figa2013-12-301-3/+3
| | * | clk: samsung: exynos5250: Add missing unpopulated mux parentsTomasz Figa2013-12-301-4/+12
| | * | clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domainTomasz Figa2013-12-301-6/+8
| | * | clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domainTomasz Figa2013-12-301-8/+17
| | * | clk: samsung: exynos5250: Make names of mux and div clocks consistentTomasz Figa2013-12-301-122/+123
| | * | clk: samsung: exynos5250: Sort definitions by registers and bitfieldTomasz Figa2013-12-301-102/+188
| | * | Merge branch 'samsung-fixes' into samsung-next-baseTomasz Figa2013-12-305-12/+18
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| | | * | clk: exynos: File scope reg_save array should depend on PM_SLEEPKrzysztof Kozlowski2013-12-301-5/+5
| | | * | clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clockAbhilash Kesavan2013-12-301-1/+2
| | | * | ARM: dts: exynos5250: Fix MDMA0 clock numberAbhilash Kesavan2013-12-301-1/+1
| | | * | clk: samsung: exynos5250: Add MDMA0 clocksAbhilash Kesavan2013-12-302-1/+6
| | | * | clk: samsung: exynos5250: Fix ACP gate register offsetAbhilash Kesavan2013-12-301-1/+1
| | | * | clk: exynos5250: fix sysmmu_mfc{l,r} gate clocksAndrew Bresticker2013-12-301-2/+2
| | | * | clk: samsung: exynos4: Correct SRC_MFC registerSeung-Woo Kim2013-12-301-1/+1
| * | | | ARM: dts: Add clock provider specific properties to max77686 nodeTomasz Figa2014-01-083-0/+3
| * | | | clk: max77686: Register OF clock providerTomasz Figa2014-01-083-0/+65
| * | | | clk: max77686: Refactor driver data handlingTomasz Figa2014-01-081-13/+14
| * | | | clk: max77686: Fix clean-up in error and remove pathsTomasz Figa2014-01-081-19/+10
| * | | | clk: max77686: Make max77686_clk_register() return struct clk *Tomasz Figa2014-01-081-7/+10
| * | | | clk: max77686: Refactor successful exit of probe functionTomasz Figa2014-01-081-2/+1
| * | | | clk: max77686: Provide .recalc_rate() operationTomasz Figa2014-01-081-0/+7
| * | | | clk: max77686: Correct callback used for checking clock statusTomasz Figa2014-01-081-2/+2
| * | | | MAINTAINERS: Add entry for Samsung SoC clock driversTomasz Figa2014-01-081-0/+6
| * | | | Merge branch 'clk-next-unregister' into clk-nextMike Turquette2013-12-3111-19/+235
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| | * \ \ \ Merge branch 'clk/clk-unregister' of git://linuxtv.org/snawrocki/samsung into...Mike Turquette2013-12-0411-19/+235
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| | | * | | | clk: Implement clk_unregisterSylwester Nawrocki2013-12-042-3/+120
| | | * | | | clk: Add common __clk_get(), __clk_put() implementationsSylwester Nawrocki2013-12-047-0/+42
| | | * | | | clkdev: Fix race condition in clock lookup from device treeSylwester Nawrocki2013-12-041-2/+10
| | | * | | | clk: Provide not locked variant of of_clk_get_from_provider()Sylwester Nawrocki2013-12-042-8/+46
| | | * | | | omap3isp: Modify clocks registration to avoid circular referencesSylwester Nawrocki2013-12-042-6/+17
| * | | | | | Merge branch 'for_3.14/keystone-clk' of git://git.kernel.org/pub/scm/linux/ke...Mike Turquette2013-12-303-12/+32
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| | * | | | | clk: keystone: gate: fix error handling on initGrygorii Strashko2013-12-101-4/+8
| | * | | | | clk: keystone: use clkod register bits for postdivMurali Karicheri2013-12-102-8/+24
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| * | | | | Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linu...Mike Turquette2013-12-294-79/+445
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| | * | | | clk: sunxi: Allwinner A20 output clock supportChen-Yu Tsai2013-12-282-0/+58
| | * | | | clk: sunxi: support better factor DT nodesEmilio López2013-12-281-0/+9
| | * | | | clk: sunxi: mod0 supportEmilio López2013-12-282-1/+61
| | * | | | clk: sunxi: add PLL5 and PLL6 supportEmilio López2013-12-282-0/+232
| | * | | | clk: sunxi: make factors_clk_setup return the clock it registersEmilio López2013-12-281-7/+8
| | * | | | clk: sunxi: add gating support to PLL1Emilio López2013-12-282-1/+3
| | * | | | clk: sunxi: clean the magic number of mux parentsEmilio López2013-12-281-2/+3
| | * | | | clk: sunxi: register factors clocks behind compositeEmilio López2013-12-283-73/+76
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