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* Merge branch 'tegra/dma-reset-rework' into next/dtOlof Johansson2013-12-26356-4794/+8489
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bringing in the tegra dma/reset framework cleanup as a base for the DT changes. * tegra/dma-reset-rework: (320 commits) spi: tegra: checking for ERR_PTR instead of NULL ASoC: tegra: update module reset list for Tegra124 clk: tegra: remove bogus PCIE_XCLK clk: tegra: remove legacy reset APIs ARM: tegra: remove legacy DMA entries from DT ARM: tegra: remove legacy clock entries from DT USB: EHCI: tegra: use reset framework Input: tegra-kbc - use reset framework serial: tegra: convert to standard DMA DT bindings serial: tegra: use reset framework spi: tegra: convert to standard DMA DT bindings spi: tegra: use reset framework staging: nvec: use reset framework i2c: tegra: use reset framework ASoC: tegra: convert to standard DMA DT bindings ASoC: tegra: allocate AHUB FIFO during probe() not startup() ASoC: tegra: call pm_runtime APIs around register accesses ASoC: tegra: use reset framework dma: tegra: register as an OF DMA controller dma: tegra: use reset framework ... Signed-off-by: Olof Johansson <olof@lixom.net>
| * spi: tegra: checking for ERR_PTR instead of NULLDan Carpenter2013-12-161-2/+2
| | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() returns NULL on error and not ERR_PTRs. I've fixed this by using dma_request_slave_channel_reason() which does return ERR_PTRs. Fixes: a915d150f68d ('spi: tegra: convert to standard DMA DT bindings') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ASoC: tegra: update module reset list for Tegra124Stephen Warren2013-12-122-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124 adds a number of extra modules into the configlink bus, which must be taken out of reset before the bus is used. Update the AHUB driver to know about these extra modules (the AHUB HW module hosts the configlink bus). Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com> Based-on-work-by: Songhee Baek <sbaek@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> --- This patch depends on "ASoC: tegra: use reset framework" to compile, which is ack'd and slated to go through a (large) topic branch in the Tegra tree. So, we can either: a) Merge that Tegra topic branch into the ASoC tree, then apply this. Note that I haven't created the topic branch yet, since I'm still waiting for DMA dependencies to be applied. b) Apply this change to the Tegra tree too. This change isn't directly related to the changes in the Tegra tree; it just makes use of the new reset controller feature that's introduced there.
| * clk: tegra: remove bogus PCIE_XCLKStephen Warren2013-12-114-15/+2
| | | | | | | | | | | | | | | | | | | | | | The "pcie_xclk" clock is not actually a clock at all, but rather a reset domain. Now that the custom Tegra module reset API has been removed, we can remove the definition of any "clocks" that existed solely to support it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: remove legacy reset APIsStephen Warren2013-12-114-70/+0
| | | | | | | | | | | | | | | | | | Now that no code uses the custom Tegra module reset API, we can remove its implementation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
| * ARM: tegra: remove legacy DMA entries from DTStephen Warren2013-12-113-39/+0
| | | | | | | | | | | | | | | | | | Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra: remove legacy clock entries from DTStephen Warren2013-12-113-32/+6
| | | | | | | | | | | | | | | | | | Now that all Tegra drivers have been converted to use the common reset framework, we can remove all the legacy DT clocks/clock-names entries for "clocks" that were only used with the old custom Tegra module reset API. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * USB: EHCI: tegra: use reset frameworkStephen Warren2013-12-111-3/+11
| | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * Input: tegra-kbc - use reset frameworkStephen Warren2013-12-111-3/+10
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * serial: tegra: convert to standard DMA DT bindingsStephen Warren2013-12-111-18/+6
| | | | | | | | | | | | | | | | | | | | | | By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * serial: tegra: use reset frameworkStephen Warren2013-12-111-4/+10
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * spi: tegra: convert to standard DMA DT bindingsStephen Warren2013-12-112-62/+34
| | | | | | | | | | | | | | | | | | | | By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * spi: tegra: use reset frameworkStephen Warren2013-12-114-15/+42
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * staging: nvec: use reset frameworkStephen Warren2013-12-112-4/+12
| | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * i2c: tegra: use reset frameworkStephen Warren2013-12-111-3/+10
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ASoC: tegra: convert to standard DMA DT bindingsStephen Warren2013-12-118-60/+42
| | | | | | | | | | | | | | | | | | | | | | | | By passing no flags when calling snd_dmaengine_pcm_register() from tegra_pcm.c, we end up using dma_request_slave_channel() rather than dmaengine_pcm_compat_request_channel(), and hence rely on the standard DMA DT bindings and stashing the DMA slave ID away during channel allocation. This means there's no need to use a custom DT property to store the slave ID. So, remove all the code that parsed it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * ASoC: tegra: allocate AHUB FIFO during probe() not startup()Stephen Warren2013-12-111-44/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only when an audio stream starts playback. This is theoretically nice for resource sharing, but makes no practical difference for any configuration the drivers currently support. However, this deferral prevents conversion to the standard DMA DT bindings, since conversion requires knowledge of the specific DMA channel to be allocated, which in turn depends on which specific FIFO was allocated. For this reason, move the FIFO allocation into probe() to allow later conversion to the standard DMA DT bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * ASoC: tegra: call pm_runtime APIs around register accessesStephen Warren2013-12-111-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Call pm_runtime_get_sync() before all register accesses; the HW requires clocks to be running when accessing registers. This hasn't been needed to date, since all register IO was performed while playback was active, and hence the ASoC core had already called pm_runtime_get(). However, an imminent future commit will allocate and set up the FIFOs and routing during probe(), when that "protection" won't be in place. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * ASoC: tegra: use reset frameworkStephen Warren2013-12-113-34/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. This change also renames "clock"/"clk" to "modules"/"mod" in symbols related to entries in configlink_clocks[], since: - We don't care about clock handles any more, but rather reset handles, so the old name isn't applicable. - It really is a list of modules on the bus, about which we currently only care about reset handles. If we start caring about any other aspect of the modules in the future, we won't have to rename all these symbols again. Note: The addition of "depends COMMON_CLOCK" is something that was missing before, not a new requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * dma: tegra: register as an OF DMA controllerStephen Warren2013-12-111-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | Call of_dma_controller_register() so that DMA clients can look up the Tegra DMA controller using standard APIs. This requires the of_xlate() function to save off the DMA slave ID, and for tegra_dma_slave_config() not to over-write this information; once DMA client drivers are converted to dma_request_slave_channel() and DT-based lookups, they won't set this field of struct dma_slave_config anymore. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * dma: tegra: use reset frameworkStephen Warren2013-12-111-3/+10
| | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com>
| * ARM: tegra: pass reset to tegra_powergate_sequence_power_up()Stephen Warren2013-12-114-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: use reset frameworkStephen Warren2013-12-115-6/+39
| | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
| * pci: tegra: use reset frameworkStephen Warren2013-12-111-14/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. The old Tegra-specific API used a struct clock to represent the module to reset. Some of the clocks retrieved during probe() were only used for reset purposes, and indeed aren't even true clocks. So, there's no need to get() them any more. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: implement a reset driverStephen Warren2013-12-116-6/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
| * ARM: tegra: select the reset frameworkStephen Warren2013-12-111-0/+2
| | | | | | | | | | | | | | | | | | The Tegra clock driver is built unconditionally when Tegra support is enabled. In order to avoid having to ifdef the forthcoming reset driver implementation, have ARCH_TEGRA select RESET_CONTROLLER. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra: update DT files to add DMA propertiesStephen Warren2013-12-113-0/+119
| | | | | | | | | | | | | | | | | | This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra: update DT files to add reset propertiesStephen Warren2013-12-114-4/+266
| | | | | | | | | | | | | | | | | | | | | | | | An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: document use of standard DMA DT bindingsStephen Warren2013-12-119-29/+73
| | | | | | | | | | | | | | | | | | | | | | Update all the Tegra DT bindings to require the standard dmas/dma-names properties rather than non-standard nvidia,dma-request-selector property. This is a DT-ABI-incompatible change. It is the second of two changes required for me to consider the Tegra DT bindings as stable, the other being the previous conversion to the common reset bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: document reset properties in DT bindingsStephen Warren2013-12-1121-9/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update all the Tegra DT bindings to require resets/reset-names properties where the HW module has reset inputs. Remove any entries from clocks or clock-names that were only required to identify reset inputs, rather than referring to real clocks. This is a DT-ABI-incompatible change. It is the first of two changes required for me to consider the Tegra DT bindings as stable, the other being conversion to the common DMA DT bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
| * ARM: tegra: add missing clock documentation to DT bindingsStephen Warren2013-12-1128-42/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
| * Merge tag 'clk-tegra-for-3.14' into for-3.14/dmas-resets-reworkStephen Warren2013-12-1120-3013/+5091
| |\ | | | | | | | | | Tegra clk branch for 3.14
| | * clk: tegra: fix __clk_lookup() return value checksWei Yongjun2013-11-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function __clk_lookup() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| | * clk: tegra: Do not print errors for clk_round_rate()Thierry Reding2013-11-281-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_round_rate() can be used by drivers to determine whether or not a frequency is supported by the clock. The current Tegra clock driver outputs an error message and a stacktrace when the requested rate isn't supported. That's fine for clk_set_rate(), but it's confusing when all the driver does is query whether or not a frequency is supported. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra: Initialize DSI low-power clocksThierry Reding2013-11-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The low-power DSI clocks are used during host-driven transactions on the DSI bus. Documentation recommends that they be children of PLLP and run at a frequency of at least 52 MHz. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra: add FUSE clock deviceAlexandre Courbot2013-11-264-1/+4
| | | | | | | | | | | | | | | | | | | | | This clock is needed to ensure the FUSE registers can be accessed without freezing the system. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
| | * clk: tegra: Properly setup PWM clock on Tegra30Thierry Reding2013-11-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | The clock for the PWM controller is slightly different from other peripheral clocks on Tegra30. The clock source mux field start at bit position 28 rather than 30. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra: Initialize secondary gr3d clock on Tegra30Thierry Reding2013-11-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | There are two GPUs on Tegra30 and each of them uses a separate clock, so the secondary clock needs to be initialized in order for the gr3d module to work properly. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra114: Initialize clocks needed for HDMIMikko Perttunen2013-11-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add disp1 and disp2 clocks to the clock initialization table. These clocks are required for display and HDMI support. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra124: add suspend/resume function for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding suspend/resume function for tegra_cpu_car_ops. We only save and restore the setting of the clock of CoreSight. Other clocks still need to be taken care by clock driver. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| | * clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_opsJoseph Lo2013-11-261-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hook the functions for CPU hotplug support. After the CPU is hot unplugged, the flow controller will handle to clock gate the CPU clock. But still need to implement an empty function to avoid warning message. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com>
| | * clk: tegra124: Add support for Tegra124 clocksPeter De Schrijver2013-11-264-0/+1771
| | | | | | | | | | | | | | | | | | Implement clock support for Tegra124. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| | * clk: tegra124: Add new peripheral clocksPeter De Schrijver2013-11-261-0/+69
| | | | | | | | | | | | | | | | | | | | | Tegra124 introduces a number of new peripheral clocks. This patch adds those to the common peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| | * clk: tegra124: Add common clk IDs to clk-id.hPeter De Schrijver2013-11-261-0/+22
| | | | | | | | | | | | | | | | | | | | | Tegra124 introduces a number of a new clocks. Introduce the corresponding the IDs for them. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| | * clk: tegra: add TEGRA_PERIPH_NO_GATEPeter De Schrijver2013-11-263-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | Tegra124 has a clock which consists of a mux and a fractional divider. Add support for this. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra: add locking to periph clksPeter De Schrijver2013-11-262-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | Tegra124 has periph clocks which share the hw register. Hence locking is required. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * clk: tegra: Add periph regs bank XPeter De Schrijver2013-11-261-0/+10
| | | | | | | | | | | | | | | | | | | | | Tegra124 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| | * clk: tegra: Add support for PLLSSPeter De Schrijver2013-11-262-2/+126
| | | | | | | | | | | | | | | | | | Tegra124 introduces a new PLL type, PLLSS. Add support for it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| | * clk: tegra: move tegra20 to common infraPeter De Schrijver2013-11-261-402/+255
| | | | | | | | | | | | | | | | | | Move tegra20 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| | * clk: tegra: move tegra30 to common infraPeter De Schrijver2013-11-261-895/+403
| | | | | | | | | | | | | | | | | | Move tegra30 to common tegra clock infrastructure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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