diff options
Diffstat (limited to 'tools/perf/arch/x86/tests')
| -rw-r--r-- | tools/perf/arch/x86/tests/Build | 2 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/arch-tests.c | 4 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/bp-modify.c | 1 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/dwarf-unwind.c | 4 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/gen-insn-x86-dat.awk | 9 | ||||
| -rwxr-xr-x | tools/perf/arch/x86/tests/gen-insn-x86-dat.sh | 9 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/insn-x86-dat-32.c | 418 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/insn-x86-dat-64.c | 546 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/insn-x86-dat-src.c | 764 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/insn-x86.c | 3 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/intel-cqm.c | 14 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c | 304 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/perf-time-to-tsc.c | 55 | ||||
| -rw-r--r-- | tools/perf/arch/x86/tests/rdpmc.c | 6 |
14 files changed, 2086 insertions, 53 deletions
diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Build index 3d83d0c6982d..2997c506550c 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -4,5 +4,5 @@ perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o perf-y += arch-tests.o perf-y += rdpmc.o perf-y += perf-time-to-tsc.o -perf-$(CONFIG_AUXTRACE) += insn-x86.o +perf-$(CONFIG_AUXTRACE) += insn-x86.o intel-pt-pkt-decoder-test.o perf-$(CONFIG_X86_64) += bp-modify.o diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/tests/arch-tests.c index d47d3f8e3c8e..6763135aec17 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -23,6 +23,10 @@ struct test arch_tests[] = { .desc = "x86 instruction decoder - new instructions", .func = test__insn_x86, }, + { + .desc = "Intel PT packet decoder", + .func = test__intel_pt_pkt_decoder, + }, #endif #if defined(__x86_64__) { diff --git a/tools/perf/arch/x86/tests/bp-modify.c b/tools/perf/arch/x86/tests/bp-modify.c index f53e4406709f..adcacf1b6609 100644 --- a/tools/perf/arch/x86/tests/bp-modify.c +++ b/tools/perf/arch/x86/tests/bp-modify.c @@ -7,6 +7,7 @@ #include <unistd.h> #include <stdio.h> #include <stdlib.h> +#include <string.h> #include <sys/ptrace.h> #include <asm/ptrace.h> #include <errno.h> diff --git a/tools/perf/arch/x86/tests/dwarf-unwind.c b/tools/perf/arch/x86/tests/dwarf-unwind.c index 6ad0a1cedb13..ef43be9b6ec2 100644 --- a/tools/perf/arch/x86/tests/dwarf-unwind.c +++ b/tools/perf/arch/x86/tests/dwarf-unwind.c @@ -3,7 +3,7 @@ #include "perf_regs.h" #include "thread.h" #include "map.h" -#include "map_groups.h" +#include "maps.h" #include "event.h" #include "debug.h" #include "tests/tests.h" @@ -27,7 +27,7 @@ static int sample_ustack(struct perf_sample *sample, sp = (unsigned long) regs[PERF_REG_X86_SP]; - map = map_groups__find(thread->mg, (u64)sp); + map = maps__find(thread->maps, (u64)sp); if (!map) { pr_debug("failed to get stack map\n"); free(buf); diff --git a/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk b/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk index a21454835cd4..1a29f6379bde 100644 --- a/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk +++ b/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk @@ -1,15 +1,8 @@ #!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0-only # gen-insn-x86-dat.awk: script to convert data for the insn-x86 test # Copyright (c) 2015, Intel Corporation. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. BEGIN { print "/*" diff --git a/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh index 2d4ef94cff98..0d0a003a9c5e 100755 --- a/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh +++ b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh @@ -1,15 +1,8 @@ #!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only # gen-insn-x86-dat: generate data for the insn-x86 test # Copyright (c) 2015, Intel Corporation. # -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. set -e diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c index fab3c6de73fa..e6461abc9e7b 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-32.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c @@ -667,6 +667,86 @@ "62 f2 55 0f 4f f4 \tvrsqrt14ss %xmm4,%xmm5,%xmm6{%k7}",}, {{0x62, 0xf2, 0xd5, 0x0f, 0x4f, 0xf4, }, 6, 0, "", "", "62 f2 d5 0f 4f f4 \tvrsqrt14sd %xmm4,%xmm5,%xmm6{%k7}",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x50, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 50 d9 \tvpdpbusd %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x50, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 50 d9 \tvpdpbusd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 50 d9 \tvpdpbusd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 50 9c c8 78 56 34 12 \tvpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x51, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 51 d9 \tvpdpbusds %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x51, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 51 d9 \tvpdpbusds %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 51 d9 \tvpdpbusds %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 51 9c c8 78 56 34 12 \tvpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6e, 0x08, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6e 08 52 d9 \tvdpbf16ps %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6e, 0x28, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6e 28 52 d9 \tvdpbf16ps %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6e 48 52 d9 \tvdpbf16ps %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6e 48 52 9c c8 78 56 34 12 \tvdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 52 d9 \tvpdpwssd %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 52 d9 \tvpdpwssd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 52 d9 \tvpdpwssd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 52 9c c8 78 56 34 12 \tvpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0x20, }, 6, 0, "", "", +"62 f2 7f 48 52 20 \tvp4dpwssd (%eax),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 48 52 a4 c8 78 56 34 12 \tvp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x53, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 53 d9 \tvpdpwssds %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x53, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 53 d9 \tvpdpwssds %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 53 d9 \tvpdpwssds %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 53 9c c8 78 56 34 12 \tvpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0x20, }, 6, 0, "", "", +"62 f2 7f 48 53 20 \tvp4dpwssds (%eax),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 48 53 a4 c8 78 56 34 12 \tvp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x7d, 0x08, 0x54, 0xd1, }, 6, 0, "", "", +"62 f2 7d 08 54 d1 \tvpopcntb %xmm1,%xmm2",}, +{{0x62, 0xf2, 0x7d, 0x28, 0x54, 0xd1, }, 6, 0, "", "", +"62 f2 7d 28 54 d1 \tvpopcntb %ymm1,%ymm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x54, 0xd1, }, 6, 0, "", "", +"62 f2 7d 48 54 d1 \tvpopcntb %zmm1,%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7d 48 54 94 c8 78 56 34 12 \tvpopcntb 0x12345678(%eax,%ecx,8),%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x08, 0x54, 0xd1, }, 6, 0, "", "", +"62 f2 fd 08 54 d1 \tvpopcntw %xmm1,%xmm2",}, +{{0x62, 0xf2, 0xfd, 0x28, 0x54, 0xd1, }, 6, 0, "", "", +"62 f2 fd 28 54 d1 \tvpopcntw %ymm1,%ymm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x54, 0xd1, }, 6, 0, "", "", +"62 f2 fd 48 54 d1 \tvpopcntw %zmm1,%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x54, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 fd 48 54 94 c8 78 56 34 12 \tvpopcntw 0x12345678(%eax,%ecx,8),%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x08, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 7d 08 55 d1 \tvpopcntd %xmm1,%xmm2",}, +{{0x62, 0xf2, 0x7d, 0x28, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 7d 28 55 d1 \tvpopcntd %ymm1,%ymm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 7d 48 55 d1 \tvpopcntd %zmm1,%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7d 48 55 94 c8 78 56 34 12 \tvpopcntd 0x12345678(%eax,%ecx,8),%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x08, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 fd 08 55 d1 \tvpopcntq %xmm1,%xmm2",}, +{{0x62, 0xf2, 0xfd, 0x28, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 fd 28 55 d1 \tvpopcntq %ymm1,%ymm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 fd 48 55 d1 \tvpopcntq %zmm1,%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 fd 48 55 94 c8 78 56 34 12 \tvpopcntq 0x12345678(%eax,%ecx,8),%zmm2",}, {{0xc4, 0xe2, 0x79, 0x59, 0xf4, }, 5, 0, "", "", "c4 e2 79 59 f4 \tvpbroadcastq %xmm4,%xmm6",}, {{0x62, 0xf2, 0x7d, 0x48, 0x59, 0xf7, }, 6, 0, "", "", @@ -681,6 +761,38 @@ "62 f2 7d 48 5b 31 \tvbroadcasti32x8 (%ecx),%zmm6",}, {{0x62, 0xf2, 0xfd, 0x48, 0x5b, 0x31, }, 6, 0, "", "", "62 f2 fd 48 5b 31 \tvbroadcasti64x4 (%ecx),%zmm6",}, +{{0x62, 0xf2, 0x7d, 0x08, 0x62, 0xd1, }, 6, 0, "", "", +"62 f2 7d 08 62 d1 \tvpexpandb %xmm1,%xmm2",}, +{{0x62, 0xf2, 0x7d, 0x28, 0x62, 0xd1, }, 6, 0, "", "", +"62 f2 7d 28 62 d1 \tvpexpandb %ymm1,%ymm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x62, 0xd1, }, 6, 0, "", "", +"62 f2 7d 48 62 d1 \tvpexpandb %zmm1,%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7d 48 62 94 c8 78 56 34 12 \tvpexpandb 0x12345678(%eax,%ecx,8),%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x08, 0x62, 0xd1, }, 6, 0, "", "", +"62 f2 fd 08 62 d1 \tvpexpandw %xmm1,%xmm2",}, +{{0x62, 0xf2, 0xfd, 0x28, 0x62, 0xd1, }, 6, 0, "", "", +"62 f2 fd 28 62 d1 \tvpexpandw %ymm1,%ymm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x62, 0xd1, }, 6, 0, "", "", +"62 f2 fd 48 62 d1 \tvpexpandw %zmm1,%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x62, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 fd 48 62 94 c8 78 56 34 12 \tvpexpandw 0x12345678(%eax,%ecx,8),%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x08, 0x63, 0xca, }, 6, 0, "", "", +"62 f2 7d 08 63 ca \tvpcompressb %xmm1,%xmm2",}, +{{0x62, 0xf2, 0x7d, 0x28, 0x63, 0xca, }, 6, 0, "", "", +"62 f2 7d 28 63 ca \tvpcompressb %ymm1,%ymm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x63, 0xca, }, 6, 0, "", "", +"62 f2 7d 48 63 ca \tvpcompressb %zmm1,%zmm2",}, +{{0x62, 0xf2, 0x7d, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7d 48 63 94 c8 78 56 34 12 \tvpcompressb %zmm2,0x12345678(%eax,%ecx,8)",}, +{{0x62, 0xf2, 0xfd, 0x08, 0x63, 0xca, }, 6, 0, "", "", +"62 f2 fd 08 63 ca \tvpcompressw %xmm1,%xmm2",}, +{{0x62, 0xf2, 0xfd, 0x28, 0x63, 0xca, }, 6, 0, "", "", +"62 f2 fd 28 63 ca \tvpcompressw %ymm1,%ymm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca, }, 6, 0, "", "", +"62 f2 fd 48 63 ca \tvpcompressw %zmm1,%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x63, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 fd 48 63 94 c8 78 56 34 12 \tvpcompressw %zmm2,0x12345678(%eax,%ecx,8)",}, {{0x62, 0xf2, 0x55, 0x48, 0x64, 0xf4, }, 6, 0, "", "", "62 f2 55 48 64 f4 \tvpblendmd %zmm4,%zmm5,%zmm6",}, {{0x62, 0xf2, 0xd5, 0x48, 0x64, 0xf4, }, 6, 0, "", "", @@ -693,6 +805,86 @@ "62 f2 55 48 66 f4 \tvpblendmb %zmm4,%zmm5,%zmm6",}, {{0x62, 0xf2, 0xd5, 0x48, 0x66, 0xf4, }, 6, 0, "", "", "62 f2 d5 48 66 f4 \tvpblendmw %zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf2, 0x6f, 0x08, 0x68, 0xd9, }, 6, 0, "", "", +"62 f2 6f 08 68 d9 \tvp2intersectd %xmm1,%xmm2,%k3",}, +{{0x62, 0xf2, 0x6f, 0x28, 0x68, 0xd9, }, 6, 0, "", "", +"62 f2 6f 28 68 d9 \tvp2intersectd %ymm1,%ymm2,%k3",}, +{{0x62, 0xf2, 0x6f, 0x48, 0x68, 0xd9, }, 6, 0, "", "", +"62 f2 6f 48 68 d9 \tvp2intersectd %zmm1,%zmm2,%k3",}, +{{0x62, 0xf2, 0x6f, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6f 48 68 9c c8 78 56 34 12 \tvp2intersectd 0x12345678(%eax,%ecx,8),%zmm2,%k3",}, +{{0x62, 0xf2, 0xef, 0x08, 0x68, 0xd9, }, 6, 0, "", "", +"62 f2 ef 08 68 d9 \tvp2intersectq %xmm1,%xmm2,%k3",}, +{{0x62, 0xf2, 0xef, 0x28, 0x68, 0xd9, }, 6, 0, "", "", +"62 f2 ef 28 68 d9 \tvp2intersectq %ymm1,%ymm2,%k3",}, +{{0x62, 0xf2, 0xef, 0x48, 0x68, 0xd9, }, 6, 0, "", "", +"62 f2 ef 48 68 d9 \tvp2intersectq %zmm1,%zmm2,%k3",}, +{{0x62, 0xf2, 0xef, 0x48, 0x68, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ef 48 68 9c c8 78 56 34 12 \tvp2intersectq 0x12345678(%eax,%ecx,8),%zmm2,%k3",}, +{{0x62, 0xf2, 0xed, 0x08, 0x70, 0xd9, }, 6, 0, "", "", +"62 f2 ed 08 70 d9 \tvpshldvw %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0xed, 0x28, 0x70, 0xd9, }, 6, 0, "", "", +"62 f2 ed 28 70 d9 \tvpshldvw %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x70, 0xd9, }, 6, 0, "", "", +"62 f2 ed 48 70 d9 \tvpshldvw %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x70, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ed 48 70 9c c8 78 56 34 12 \tvpshldvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x71, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 71 d9 \tvpshldvd %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x71, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 71 d9 \tvpshldvd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x71, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 71 d9 \tvpshldvd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 71 9c c8 78 56 34 12 \tvpshldvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x08, 0x71, 0xd9, }, 6, 0, "", "", +"62 f2 ed 08 71 d9 \tvpshldvq %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0xed, 0x28, 0x71, 0xd9, }, 6, 0, "", "", +"62 f2 ed 28 71 d9 \tvpshldvq %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x71, 0xd9, }, 6, 0, "", "", +"62 f2 ed 48 71 d9 \tvpshldvq %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x71, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ed 48 71 9c c8 78 56 34 12 \tvpshldvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6f, 0x08, 0x72, 0xd9, }, 6, 0, "", "", +"62 f2 6f 08 72 d9 \tvcvtne2ps2bf16 %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6f, 0x28, 0x72, 0xd9, }, 6, 0, "", "", +"62 f2 6f 28 72 d9 \tvcvtne2ps2bf16 %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6f, 0x48, 0x72, 0xd9, }, 6, 0, "", "", +"62 f2 6f 48 72 d9 \tvcvtne2ps2bf16 %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6f, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6f 48 72 9c c8 78 56 34 12 \tvcvtne2ps2bf16 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x7e, 0x08, 0x72, 0xd1, }, 6, 0, "", "", +"62 f2 7e 08 72 d1 \tvcvtneps2bf16 %xmm1,%xmm2",}, +{{0x62, 0xf2, 0x7e, 0x28, 0x72, 0xd1, }, 6, 0, "", "", +"62 f2 7e 28 72 d1 \tvcvtneps2bf16 %ymm1,%xmm2",}, +{{0x62, 0xf2, 0x7e, 0x48, 0x72, 0xd1, }, 6, 0, "", "", +"62 f2 7e 48 72 d1 \tvcvtneps2bf16 %zmm1,%ymm2",}, +{{0x62, 0xf2, 0x7e, 0x48, 0x72, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7e 48 72 94 c8 78 56 34 12 \tvcvtneps2bf16 0x12345678(%eax,%ecx,8),%ymm2",}, +{{0x62, 0xf2, 0xed, 0x08, 0x72, 0xd9, }, 6, 0, "", "", +"62 f2 ed 08 72 d9 \tvpshrdvw %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0xed, 0x28, 0x72, 0xd9, }, 6, 0, "", "", +"62 f2 ed 28 72 d9 \tvpshrdvw %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x72, 0xd9, }, 6, 0, "", "", +"62 f2 ed 48 72 d9 \tvpshrdvw %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x72, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ed 48 72 9c c8 78 56 34 12 \tvpshrdvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 73 d9 \tvpshrdvd %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 73 d9 \tvpshrdvd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 73 d9 \tvpshrdvd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 73 9c c8 78 56 34 12 \tvpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x08, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 ed 08 73 d9 \tvpshrdvq %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0xed, 0x28, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 ed 28 73 d9 \tvpshrdvq %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 ed 48 73 d9 \tvpshrdvq %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ed 48 73 9c c8 78 56 34 12 \tvpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, {{0x62, 0xf2, 0x55, 0x48, 0x75, 0xf4, }, 6, 0, "", "", "62 f2 55 48 75 f4 \tvpermi2b %zmm4,%zmm5,%zmm6",}, {{0x62, 0xf2, 0xd5, 0x48, 0x75, 0xf4, }, 6, 0, "", "", @@ -745,6 +937,14 @@ "62 f2 55 48 8d f4 \tvpermb %zmm4,%zmm5,%zmm6",}, {{0x62, 0xf2, 0xd5, 0x48, 0x8d, 0xf4, }, 6, 0, "", "", "62 f2 d5 48 8d f4 \tvpermw %zmm4,%zmm5,%zmm6",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x8f, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 8f d9 \tvpshufbitqmb %xmm1,%xmm2,%k3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x8f, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 8f d9 \tvpshufbitqmb %ymm1,%ymm2,%k3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x8f, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 8f d9 \tvpshufbitqmb %zmm1,%zmm2,%k3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x8f, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 8f 9c c8 78 56 34 12 \tvpshufbitqmb 0x12345678(%eax,%ecx,8),%zmm2,%k3",}, {{0xc4, 0xe2, 0x69, 0x90, 0x4c, 0x7d, 0x02, }, 7, 0, "", "", "c4 e2 69 90 4c 7d 02 \tvpgatherdd %xmm2,0x2(%ebp,%xmm7,2),%xmm1",}, {{0xc4, 0xe2, 0xe9, 0x90, 0x4c, 0x7d, 0x04, }, 7, 0, "", "", @@ -761,6 +961,38 @@ "62 f2 7d 49 91 b4 fd 7b 00 00 00 \tvpgatherqd 0x7b(%ebp,%zmm7,8),%ymm6{%k1}",}, {{0x62, 0xf2, 0xfd, 0x49, 0x91, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", "62 f2 fd 49 91 b4 fd 7b 00 00 00 \tvpgatherqq 0x7b(%ebp,%zmm7,8),%zmm6{%k1}",}, +{{0xc4, 0xe2, 0x69, 0x9a, 0xd9, }, 5, 0, "", "", +"c4 e2 69 9a d9 \tvfmsub132ps %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0x9a, 0xd9, }, 5, 0, "", "", +"c4 e2 6d 9a d9 \tvfmsub132ps %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x9a, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 9a d9 \tvfmsub132ps %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x9a, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 9a 9c c8 78 56 34 12 \tvfmsub132ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0xe9, 0x9a, 0xd9, }, 5, 0, "", "", +"c4 e2 e9 9a d9 \tvfmsub132pd %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0xed, 0x9a, 0xd9, }, 5, 0, "", "", +"c4 e2 ed 9a d9 \tvfmsub132pd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x9a, 0xd9, }, 6, 0, "", "", +"62 f2 ed 48 9a d9 \tvfmsub132pd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x9a, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ed 48 9a 9c c8 78 56 34 12 \tvfmsub132pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x9a, 0x20, }, 6, 0, "", "", +"62 f2 7f 48 9a 20 \tv4fmaddps (%eax),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x9a, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 48 9a a4 c8 78 56 34 12 \tv4fmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",}, +{{0xc4, 0xe2, 0x69, 0x9b, 0xd9, }, 5, 0, "", "", +"c4 e2 69 9b d9 \tvfmsub132ss %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x69, 0x9b, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"c4 e2 69 9b 9c c8 78 56 34 12 \tvfmsub132ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0xe9, 0x9b, 0xd9, }, 5, 0, "", "", +"c4 e2 e9 9b d9 \tvfmsub132sd %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0xe9, 0x9b, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"c4 e2 e9 9b 9c c8 78 56 34 12 \tvfmsub132sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x7f, 0x08, 0x9b, 0x20, }, 6, 0, "", "", +"62 f2 7f 08 9b 20 \tv4fmaddss (%eax),%xmm0,%xmm4",}, +{{0x62, 0xf2, 0x7f, 0x08, 0x9b, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 08 9b a4 c8 78 56 34 12 \tv4fmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4",}, {{0x62, 0xf2, 0x7d, 0x49, 0xa0, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", "62 f2 7d 49 a0 b4 fd 7b 00 00 00 \tvpscatterdd %zmm6,0x7b(%ebp,%zmm7,8){%k1}",}, {{0x62, 0xf2, 0xfd, 0x49, 0xa0, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", @@ -777,6 +1009,38 @@ "62 f2 7d 49 a3 b4 fd 7b 00 00 00 \tvscatterqps %ymm6,0x7b(%ebp,%zmm7,8){%k1}",}, {{0x62, 0xf2, 0xfd, 0x49, 0xa3, 0xb4, 0xfd, 0x7b, 0x00, 0x00, 0x00, }, 11, 0, "", "", "62 f2 fd 49 a3 b4 fd 7b 00 00 00 \tvscatterqpd %zmm6,0x7b(%ebp,%zmm7,8){%k1}",}, +{{0xc4, 0xe2, 0x69, 0xaa, 0xd9, }, 5, 0, "", "", +"c4 e2 69 aa d9 \tvfmsub213ps %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xaa, 0xd9, }, 5, 0, "", "", +"c4 e2 6d aa d9 \tvfmsub213ps %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xaa, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 aa d9 \tvfmsub213ps %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xaa, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 aa 9c c8 78 56 34 12 \tvfmsub213ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0xe9, 0xaa, 0xd9, }, 5, 0, "", "", +"c4 e2 e9 aa d9 \tvfmsub213pd %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0xed, 0xaa, 0xd9, }, 5, 0, "", "", +"c4 e2 ed aa d9 \tvfmsub213pd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0xaa, 0xd9, }, 6, 0, "", "", +"62 f2 ed 48 aa d9 \tvfmsub213pd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0xaa, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ed 48 aa 9c c8 78 56 34 12 \tvfmsub213pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x7f, 0x48, 0xaa, 0x20, }, 6, 0, "", "", +"62 f2 7f 48 aa 20 \tv4fnmaddps (%eax),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x7f, 0x48, 0xaa, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 48 aa a4 c8 78 56 34 12 \tv4fnmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",}, +{{0xc4, 0xe2, 0x69, 0xab, 0xd9, }, 5, 0, "", "", +"c4 e2 69 ab d9 \tvfmsub213ss %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x69, 0xab, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"c4 e2 69 ab 9c c8 78 56 34 12 \tvfmsub213ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0xe9, 0xab, 0xd9, }, 5, 0, "", "", +"c4 e2 e9 ab d9 \tvfmsub213sd %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0xe9, 0xab, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"c4 e2 e9 ab 9c c8 78 56 34 12 \tvfmsub213sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x7f, 0x08, 0xab, 0x20, }, 6, 0, "", "", +"62 f2 7f 08 ab 20 \tv4fnmaddss (%eax),%xmm0,%xmm4",}, +{{0x62, 0xf2, 0x7f, 0x08, 0xab, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 08 ab a4 c8 78 56 34 12 \tv4fnmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4",}, {{0x62, 0xf2, 0xd5, 0x48, 0xb4, 0xf4, }, 6, 0, "", "", "62 f2 d5 48 b4 f4 \tvpmadd52luq %zmm4,%zmm5,%zmm6",}, {{0x62, 0xf2, 0xd5, 0x48, 0xb5, 0xf4, }, 6, 0, "", "", @@ -805,6 +1069,50 @@ "62 f2 4d 0f cd fd \tvrsqrt28ss %xmm5,%xmm6,%xmm7{%k7}",}, {{0x62, 0xf2, 0xcd, 0x0f, 0xcd, 0xfd, }, 6, 0, "", "", "62 f2 cd 0f cd fd \tvrsqrt28sd %xmm5,%xmm6,%xmm7{%k7}",}, +{{0x66, 0x0f, 0x38, 0xcf, 0xd9, }, 5, 0, "", "", +"66 0f 38 cf d9 \tgf2p8mulb %xmm1,%xmm3",}, +{{0x66, 0x0f, 0x38, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"66 0f 38 cf 9c c8 78 56 34 12 \tgf2p8mulb 0x12345678(%eax,%ecx,8),%xmm3",}, +{{0xc4, 0xe2, 0x69, 0xcf, 0xd9, }, 5, 0, "", "", +"c4 e2 69 cf d9 \tvgf2p8mulb %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xcf, 0xd9, }, 5, 0, "", "", +"c4 e2 6d cf d9 \tvgf2p8mulb %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xcf, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 cf d9 \tvgf2p8mulb %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 cf 9c c8 78 56 34 12 \tvgf2p8mulb 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xdc, 0xd9, }, 5, 0, "", "", +"c4 e2 69 dc d9 \tvaesenc %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xdc, 0xd9, }, 5, 0, "", "", +"c4 e2 6d dc d9 \tvaesenc %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdc, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 dc d9 \tvaesenc %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdc, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 dc 9c c8 78 56 34 12 \tvaesenc 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xdd, 0xd9, }, 5, 0, "", "", +"c4 e2 69 dd d9 \tvaesenclast %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xdd, 0xd9, }, 5, 0, "", "", +"c4 e2 6d dd d9 \tvaesenclast %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdd, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 dd d9 \tvaesenclast %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdd, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 dd 9c c8 78 56 34 12 \tvaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xde, 0xd9, }, 5, 0, "", "", +"c4 e2 69 de d9 \tvaesdec %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xde, 0xd9, }, 5, 0, "", "", +"c4 e2 6d de d9 \tvaesdec %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 de d9 \tvaesdec %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 de 9c c8 78 56 34 12 \tvaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xdf, 0xd9, }, 5, 0, "", "", +"c4 e2 69 df d9 \tvaesdeclast %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xdf, 0xd9, }, 5, 0, "", "", +"c4 e2 6d df d9 \tvaesdeclast %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 df d9 \tvaesdeclast %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 df 9c c8 78 56 34 12 \tvaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, {{0x62, 0xf3, 0x4d, 0x48, 0x03, 0xfd, 0x12, }, 7, 0, "", "", "62 f3 4d 48 03 fd 12 \tvalignd $0x12,%zmm5,%zmm6,%zmm7",}, {{0x62, 0xf3, 0xcd, 0x48, 0x03, 0xfd, 0x12, }, 7, 0, "", "", @@ -905,6 +1213,12 @@ "62 f3 4d 48 43 fd 12 \tvshufi32x4 $0x12,%zmm5,%zmm6,%zmm7",}, {{0x62, 0xf3, 0xcd, 0x48, 0x43, 0xfd, 0x12, }, 7, 0, "", "", "62 f3 cd 48 43 fd 12 \tvshufi64x2 $0x12,%zmm5,%zmm6,%zmm7",}, +{{0xc4, 0xe3, 0x69, 0x44, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 69 44 d9 12 \tvpclmulqdq $0x12,%xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe3, 0x6d, 0x44, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 6d 44 d9 12 \tvpclmulqdq $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0x6d, 0x48, 0x44, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 48 44 d9 12 \tvpclmulqdq $0x12,%zmm1,%zmm2,%zmm3",}, {{0x62, 0xf3, 0x4d, 0x48, 0x50, 0xfd, 0x12, }, 7, 0, "", "", "62 f3 4d 48 50 fd 12 \tvrangeps $0x12,%zmm5,%zmm6,%zmm7",}, {{0x62, 0xf3, 0xcd, 0x48, 0x50, 0xfd, 0x12, }, 7, 0, "", "", @@ -937,6 +1251,58 @@ "62 f3 7d 08 67 ef 12 \tvfpclassss $0x12,%xmm7,%k5",}, {{0x62, 0xf3, 0xfd, 0x08, 0x67, 0xef, 0x12, }, 7, 0, "", "", "62 f3 fd 08 67 ef 12 \tvfpclasssd $0x12,%xmm7,%k5",}, +{{0x62, 0xf3, 0xed, 0x08, 0x70, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 70 d9 12 \tvpshldw $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x70, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 70 d9 12 \tvpshldw $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x70, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 70 d9 12 \tvpshldw $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf3, 0x6d, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 08 71 d9 12 \tvpshldd $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0x6d, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 28 71 d9 12 \tvpshldd $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0x6d, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 48 71 d9 12 \tvpshldd $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf3, 0xed, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 71 d9 12 \tvpshldq $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 71 d9 12 \tvpshldq $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 71 d9 12 \tvpshldq $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf3, 0xed, 0x08, 0x72, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 72 d9 12 \tvpshrdw $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x72, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 72 d9 12 \tvpshrdw $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x72, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 72 d9 12 \tvpshrdw $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf3, 0x6d, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 08 73 d9 12 \tvpshrdd $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0x6d, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 28 73 d9 12 \tvpshrdd $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0x6d, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 48 73 d9 12 \tvpshrdd $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf3, 0xed, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 73 d9 12 \tvpshrdq $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 73 d9 12 \tvpshrdq $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 73 d9 12 \tvpshrdq $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x66, 0x0f, 0x3a, 0xce, 0xd9, 0x12, }, 6, 0, "", "", +"66 0f 3a ce d9 12 \tgf2p8affineqb $0x12,%xmm1,%xmm3",}, +{{0xc4, 0xe3, 0xe9, 0xce, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 e9 ce d9 12 \tvgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe3, 0xed, 0xce, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 ed ce d9 12 \tvgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0xce, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 ce d9 12 \tvgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x66, 0x0f, 0x3a, 0xcf, 0xd9, 0x12, }, 6, 0, "", "", +"66 0f 3a cf d9 12 \tgf2p8affineinvqb $0x12,%xmm1,%xmm3",}, +{{0xc4, 0xe3, 0xe9, 0xcf, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 e9 cf d9 12 \tvgf2p8affineinvqb $0x12,%xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe3, 0xed, 0xcf, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 ed cf d9 12 \tvgf2p8affineinvqb $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0xcf, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 cf d9 12 \tvgf2p8affineinvqb $0x12,%zmm1,%zmm2,%zmm3",}, {{0x62, 0xf1, 0x4d, 0x48, 0x72, 0xc5, 0x12, }, 7, 0, "", "", "62 f1 4d 48 72 c5 12 \tvprord $0x12,%zmm5,%zmm6",}, {{0x62, 0xf1, 0xcd, 0x48, 0x72, 0xc5, 0x12, }, 7, 0, "", "", @@ -1647,6 +2013,12 @@ "0f ae 30 \txsaveopt (%eax)",}, {{0x0f, 0xae, 0xf0, }, 3, 0, "", "", "0f ae f0 \tmfence ",}, +{{0x0f, 0x1c, 0x00, }, 3, 0, "", "", +"0f 1c 00 \tcldemote (%eax)",}, +{{0x0f, 0x1c, 0x05, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", +"0f 1c 05 78 56 34 12 \tcldemote 0x12345678",}, +{{0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%eax,%ecx,8)",}, {{0x0f, 0xc7, 0x20, }, 3, 0, "", "", "0f c7 20 \txsavec (%eax)",}, {{0x0f, 0xc7, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "", @@ -1677,3 +2049,49 @@ "f3 0f ae 25 78 56 34 12 \tptwritel 0x12345678",}, {{0xf3, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", "f3 0f ae a4 c8 78 56 34 12 \tptwritel 0x12345678(%eax,%ecx,8)",}, +{{0x66, 0x0f, 0xae, 0xf3, }, 4, 0, "", "", +"66 0f ae f3 \ttpause %ebx",}, +{{0x67, 0xf3, 0x0f, 0xae, 0xf0, }, 5, 0, "", "", +"67 f3 0f ae f0 \tumonitor %ax",}, +{{0xf3, 0x0f, 0xae, 0xf0, }, 4, 0, "", "", +"f3 0f ae f0 \tumonitor %eax",}, +{{0xf2, 0x0f, 0xae, 0xf0, }, 4, 0, "", "", +"f2 0f ae f0 \tumwait %eax",}, +{{0x0f, 0x38, 0xf9, 0x03, }, 4, 0, "", "", +"0f 38 f9 03 \tmovdiri %eax,(%ebx)",}, +{{0x0f, 0x38, 0xf9, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f 38 f9 88 78 56 34 12 \tmovdiri %ecx,0x12345678(%eax)",}, +{{0x66, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "", +"66 0f 38 f8 18 \tmovdir64b (%eax),%ebx",}, +{{0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%eax),%ecx",}, +{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x1c, }, 6, 0, "", "", +"67 66 0f 38 f8 1c \tmovdir64b (%si),%bx",}, +{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x8c, 0x34, 0x12, }, 8, 0, "", "", +"67 66 0f 38 f8 8c 34 12 \tmovdir64b 0x1234(%si),%cx",}, +{{0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "", +"f2 0f 38 f8 18 \tenqcmd (%eax),%ebx",}, +{{0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%eax),%ecx",}, +{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x1c, }, 6, 0, "", "", +"67 f2 0f 38 f8 1c \tenqcmd (%si),%bx",}, +{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x8c, 0x34, 0x12, }, 8, 0, "", "", +"67 f2 0f 38 f8 8c 34 12 \tenqcmd 0x1234(%si),%cx",}, +{{0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "", +"f3 0f 38 f8 18 \tenqcmds (%eax),%ebx",}, +{{0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%eax),%ecx",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x1c, }, 6, 0, "", "", +"67 f3 0f 38 f8 1c \tenqcmds (%si),%bx",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x8c, 0x34, 0x12, }, 8, 0, "", "", +"67 f3 0f 38 f8 8c 34 12 \tenqcmds 0x1234(%si),%cx",}, +{{0x0f, 0x01, 0xcf, }, 3, 0, "", "", +"0f 01 cf \tencls ",}, +{{0x0f, 0x01, 0xd7, }, 3, 0, "", "", +"0f 01 d7 \tenclu ",}, +{{0x0f, 0x01, 0xc0, }, 3, 0, "", "", +"0f 01 c0 \tenclv ",}, +{{0x0f, 0x01, 0xc5, }, 3, 0, "", "", +"0f 01 c5 \tpconfig ",}, +{{0xf3, 0x0f, 0x09, }, 3, 0, "", "", +"f3 0f 09 \twbnoinvd ",}, diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c index c57f34603b9b..567ecccfad7c 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-64.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c @@ -587,6 +587,112 @@ "62 02 35 07 4f d0 \tvrsqrt14ss %xmm24,%xmm25,%xmm26{%k7}",}, {{0x62, 0x02, 0xb5, 0x07, 0x4f, 0xd0, }, 6, 0, "", "", "62 02 b5 07 4f d0 \tvrsqrt14sd %xmm24,%xmm25,%xmm26{%k7}",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x50, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 50 d9 \tvpdpbusd %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x50, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 50 d9 \tvpdpbusd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 50 d9 \tvpdpbusd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x50, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 50 9c c8 78 56 34 12 \tvpdpbusd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x50, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 50 9c c8 78 56 34 12 \tvpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x51, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 51 d9 \tvpdpbusds %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x51, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 51 d9 \tvpdpbusds %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 51 d9 \tvpdpbusds %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x51, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 51 9c c8 78 56 34 12 \tvpdpbusds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x51, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 51 9c c8 78 56 34 12 \tvpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6e, 0x08, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6e 08 52 d9 \tvdpbf16ps %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6e, 0x28, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6e 28 52 d9 \tvdpbf16ps %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6e 48 52 d9 \tvdpbf16ps %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6e, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6e 48 52 9c c8 78 56 34 12 \tvdpbf16ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6e, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6e 48 52 9c c8 78 56 34 12 \tvdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 52 d9 \tvpdpwssd %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 52 d9 \tvpdpwssd %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 52 d9 \tvpdpwssd %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 52 9c c8 78 56 34 12 \tvpdpwssd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x52, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 52 9c c8 78 56 34 12 \tvpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0x20, }, 6, 0, "", "", +"62 f2 7f 48 52 20 \tvp4dpwssd (%rax),%zmm0,%zmm4",}, +{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x52, 0x20, }, 7, 0, "", "", +"67 62 f2 7f 48 52 20 \tvp4dpwssd (%eax),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x52, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 48 52 a4 c8 78 56 34 12 \tvp4dpwssd 0x12345678(%rax,%rcx,8),%zmm0,%zmm4",}, +{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x52, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 7f 48 52 a4 c8 78 56 34 12 \tvp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x53, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 53 d9 \tvpdpwssds %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x53, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 53 d9 \tvpdpwssds %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 53 d9 \tvpdpwssds %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x53, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 53 9c c8 78 56 34 12 \tvpdpwssds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x53, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 53 9c c8 78 56 34 12 \tvpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0x20, }, 6, 0, "", "", +"62 f2 7f 48 53 20 \tvp4dpwssds (%rax),%zmm0,%zmm4",}, +{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x53, 0x20, }, 7, 0, "", "", +"67 62 f2 7f 48 53 20 \tvp4dpwssds (%eax),%zmm0,%zmm4",}, +{{0x62, 0xf2, 0x7f, 0x48, 0x53, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 7f 48 53 a4 c8 78 56 34 12 \tvp4dpwssds 0x12345678(%rax,%rcx,8),%zmm0,%zmm4",}, +{{0x67, 0x62, 0xf2, 0x7f, 0x48, 0x53, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 7f 48 53 a4 c8 78 56 34 12 \tvp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4",}, 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0, "", "", +"62 f2 fd 08 55 d1 \tvpopcntq %xmm1,%xmm2",}, +{{0x62, 0xf2, 0xfd, 0x28, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 fd 28 55 d1 \tvpopcntq %ymm1,%ymm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0xd1, }, 6, 0, "", "", +"62 f2 fd 48 55 d1 \tvpopcntq %zmm1,%zmm2",}, +{{0x62, 0xf2, 0xfd, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 fd 48 55 94 c8 78 56 34 12 \tvpopcntq 0x12345678(%rax,%rcx,8),%zmm2",}, +{{0x67, 0x62, 0xf2, 0xfd, 0x48, 0x55, 0x94, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 fd 48 55 94 c8 78 56 34 12 \tvpopcntq 0x12345678(%eax,%ecx,8),%zmm2",}, {{0xc4, 0xe2, 0x79, 0x59, 0xf4, }, 5, 0, "", "", "c4 e2 79 59 f4 \tvpbroadcastq %xmm4,%xmm6",}, {{0x62, 0x02, 0x7d, 0x48, 0x59, 0xd3, }, 6, 0, "", "", @@ -601,6 +707,46 @@ "62 62 7d 48 5b 21 \tvbroadcasti32x8 (%rcx),%zmm28",}, {{0x62, 0x62, 0xfd, 0x48, 0x5b, 0x11, }, 6, 0, "", "", "62 62 fd 48 5b 11 \tvbroadcasti64x4 (%rcx),%zmm26",}, +{{0x62, 0xf2, 0x7d, 0x08, 0x62, 0xd1, }, 6, 0, "", "", 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0xf2, 0x6d, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 73 9c c8 78 56 34 12 \tvpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x08, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 ed 08 73 d9 \tvpshrdvq %xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf2, 0xed, 0x28, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 ed 28 73 d9 \tvpshrdvq %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x73, 0xd9, }, 6, 0, "", "", +"62 f2 ed 48 73 d9 \tvpshrdvq %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0xed, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 ed 48 73 9c c8 78 56 34 12 \tvpshrdvq 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0xed, 0x48, 0x73, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 ed 48 73 9c c8 78 56 34 12 \tvpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, {{0x62, 0x02, 0x35, 0x40, 0x75, 0xd0, }, 6, 0, "", "", "62 02 35 40 75 d0 \tvpermi2b %zmm24,%zmm25,%zmm26",}, {{0x62, 0x02, 0xa5, 0x40, 0x75, 0xe2, }, 6, 0, "", "", @@ -667,6 +913,16 @@ "62 02 25 40 8d e2 \tvpermb %zmm26,%zmm27,%zmm28",}, {{0x62, 0x02, 0xa5, 0x40, 0x8d, 0xe2, }, 6, 0, "", "", "62 02 a5 40 8d e2 \tvpermw %zmm26,%zmm27,%zmm28",}, +{{0x62, 0xf2, 0x6d, 0x08, 0x8f, 0xd9, }, 6, 0, "", "", +"62 f2 6d 08 8f d9 \tvpshufbitqmb %xmm1,%xmm2,%k3",}, +{{0x62, 0xf2, 0x6d, 0x28, 0x8f, 0xd9, }, 6, 0, "", "", +"62 f2 6d 28 8f d9 \tvpshufbitqmb %ymm1,%ymm2,%k3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x8f, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 8f d9 \tvpshufbitqmb %zmm1,%zmm2,%k3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0x8f, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 8f 9c c8 78 56 34 12 \tvpshufbitqmb 0x12345678(%rax,%rcx,8),%zmm2,%k3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0x8f, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 8f 9c c8 78 56 34 12 \tvpshufbitqmb 0x12345678(%eax,%ecx,8),%zmm2,%k3",}, {{0xc4, 0xe2, 0x69, 0x90, 0x4c, 0x7d, 0x02, }, 7, 0, "", "", "c4 e2 69 90 4c 7d 02 \tvpgatherdd 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"62 02 15 07 cd f4 \tvrsqrt28ss %xmm28,%xmm29,%xmm30{%k7}",}, {{0x62, 0x02, 0xad, 0x07, 0xcd, 0xd9, }, 6, 0, "", "", "62 02 ad 07 cd d9 \tvrsqrt28sd %xmm25,%xmm26,%xmm27{%k7}",}, +{{0x66, 0x0f, 0x38, 0xcf, 0xd9, }, 5, 0, "", "", +"66 0f 38 cf d9 \tgf2p8mulb %xmm1,%xmm3",}, +{{0x66, 0x0f, 0x38, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"66 0f 38 cf 9c c8 78 56 34 12 \tgf2p8mulb 0x12345678(%rax,%rcx,8),%xmm3",}, +{{0x67, 0x66, 0x0f, 0x38, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"67 66 0f 38 cf 9c c8 78 56 34 12 \tgf2p8mulb 0x12345678(%eax,%ecx,8),%xmm3",}, +{{0xc4, 0xe2, 0x69, 0xcf, 0xd9, }, 5, 0, "", "", +"c4 e2 69 cf d9 \tvgf2p8mulb %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xcf, 0xd9, }, 5, 0, "", "", +"c4 e2 6d cf d9 \tvgf2p8mulb %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xcf, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 cf d9 \tvgf2p8mulb %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 cf 9c c8 78 56 34 12 \tvgf2p8mulb 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xcf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 cf 9c c8 78 56 34 12 \tvgf2p8mulb 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xdc, 0xd9, }, 5, 0, "", "", +"c4 e2 69 dc d9 \tvaesenc %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xdc, 0xd9, }, 5, 0, "", "", +"c4 e2 6d dc d9 \tvaesenc %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdc, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 dc d9 \tvaesenc %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdc, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 dc 9c c8 78 56 34 12 \tvaesenc 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xdc, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 dc 9c c8 78 56 34 12 \tvaesenc 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xdd, 0xd9, }, 5, 0, "", "", +"c4 e2 69 dd d9 \tvaesenclast %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xdd, 0xd9, }, 5, 0, "", "", +"c4 e2 6d dd d9 \tvaesenclast %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdd, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 dd d9 \tvaesenclast %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdd, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 dd 9c c8 78 56 34 12 \tvaesenclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xdd, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 dd 9c c8 78 56 34 12 \tvaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xde, 0xd9, }, 5, 0, "", "", +"c4 e2 69 de d9 \tvaesdec %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xde, 0xd9, }, 5, 0, "", "", +"c4 e2 6d de d9 \tvaesdec %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 de d9 \tvaesdec %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xde, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 de 9c c8 78 56 34 12 \tvaesdec 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xde, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 de 9c c8 78 56 34 12 \tvaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, +{{0xc4, 0xe2, 0x69, 0xdf, 0xd9, }, 5, 0, "", "", +"c4 e2 69 df d9 \tvaesdeclast %xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe2, 0x6d, 0xdf, 0xd9, }, 5, 0, "", "", +"c4 e2 6d df d9 \tvaesdeclast %ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0xd9, }, 6, 0, "", "", +"62 f2 6d 48 df d9 \tvaesdeclast %zmm1,%zmm2,%zmm3",}, +{{0x62, 0xf2, 0x6d, 0x48, 0xdf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 11, 0, "", "", +"62 f2 6d 48 df 9c c8 78 56 34 12 \tvaesdeclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3",}, +{{0x67, 0x62, 0xf2, 0x6d, 0x48, 0xdf, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 12, 0, "", "", +"67 62 f2 6d 48 df 9c c8 78 56 34 12 \tvaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3",}, {{0x62, 0x03, 0x15, 0x40, 0x03, 0xf4, 0x12, }, 7, 0, "", "", "62 03 15 40 03 f4 12 \tvalignd $0x12,%zmm28,%zmm29,%zmm30",}, {{0x62, 0x03, 0xad, 0x40, 0x03, 0xd9, 0x12, }, 7, 0, "", "", @@ -827,6 +1235,14 @@ "62 03 2d 40 43 d9 12 \tvshufi32x4 $0x12,%zmm25,%zmm26,%zmm27",}, {{0x62, 0x03, 0x95, 0x40, 0x43, 0xf4, 0x12, }, 7, 0, "", "", "62 03 95 40 43 f4 12 \tvshufi64x2 $0x12,%zmm28,%zmm29,%zmm30",}, +{{0xc4, 0xe3, 0x69, 0x44, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 69 44 d9 12 \tvpclmulqdq $0x12,%xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe3, 0x6d, 0x44, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 6d 44 d9 12 \tvpclmulqdq $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0x6d, 0x48, 0x44, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 48 44 d9 12 \tvpclmulqdq $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0x2d, 0x40, 0x44, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 2d 40 44 d9 12 \tvpclmulqdq $0x12,%zmm25,%zmm26,%zmm27",}, {{0x62, 0x03, 0x2d, 0x40, 0x50, 0xd9, 0x12, }, 7, 0, "", "", "62 03 2d 40 50 d9 12 \tvrangeps $0x12,%zmm25,%zmm26,%zmm27",}, {{0x62, 0x03, 0x95, 0x40, 0x50, 0xf4, 0x12, }, 7, 0, "", "", @@ -859,6 +1275,74 @@ "62 93 7d 08 67 eb 12 \tvfpclassss $0x12,%xmm27,%k5",}, {{0x62, 0x93, 0xfd, 0x08, 0x67, 0xee, 0x12, }, 7, 0, "", "", "62 93 fd 08 67 ee 12 \tvfpclasssd $0x12,%xmm30,%k5",}, +{{0x62, 0xf3, 0xed, 0x08, 0x70, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 70 d9 12 \tvpshldw $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x70, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 70 d9 12 \tvpshldw $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x70, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 70 d9 12 \tvpshldw $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0xad, 0x40, 0x70, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 ad 40 70 d9 12 \tvpshldw $0x12,%zmm25,%zmm26,%zmm27",}, +{{0x62, 0xf3, 0x6d, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 08 71 d9 12 \tvpshldd $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0x6d, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 28 71 d9 12 \tvpshldd $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0x6d, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 48 71 d9 12 \tvpshldd $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0x2d, 0x40, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 2d 40 71 d9 12 \tvpshldd $0x12,%zmm25,%zmm26,%zmm27",}, +{{0x62, 0xf3, 0xed, 0x08, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 71 d9 12 \tvpshldq $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 71 d9 12 \tvpshldq $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 71 d9 12 \tvpshldq $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0xad, 0x40, 0x71, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 ad 40 71 d9 12 \tvpshldq $0x12,%zmm25,%zmm26,%zmm27",}, +{{0x62, 0xf3, 0xed, 0x08, 0x72, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 72 d9 12 \tvpshrdw $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x72, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 72 d9 12 \tvpshrdw $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x72, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 72 d9 12 \tvpshrdw $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0xad, 0x40, 0x72, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 ad 40 72 d9 12 \tvpshrdw $0x12,%zmm25,%zmm26,%zmm27",}, +{{0x62, 0xf3, 0x6d, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 08 73 d9 12 \tvpshrdd $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0x6d, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 28 73 d9 12 \tvpshrdd $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0x6d, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 6d 48 73 d9 12 \tvpshrdd $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0x2d, 0x40, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 2d 40 73 d9 12 \tvpshrdd $0x12,%zmm25,%zmm26,%zmm27",}, +{{0x62, 0xf3, 0xed, 0x08, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 08 73 d9 12 \tvpshrdq $0x12,%xmm1,%xmm2,%xmm3",}, +{{0x62, 0xf3, 0xed, 0x28, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 28 73 d9 12 \tvpshrdq $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 73 d9 12 \tvpshrdq $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0xad, 0x40, 0x73, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 ad 40 73 d9 12 \tvpshrdq $0x12,%zmm25,%zmm26,%zmm27",}, +{{0x66, 0x0f, 0x3a, 0xce, 0xd9, 0x12, }, 6, 0, "", "", +"66 0f 3a ce d9 12 \tgf2p8affineqb $0x12,%xmm1,%xmm3",}, +{{0xc4, 0xe3, 0xe9, 0xce, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 e9 ce d9 12 \tvgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe3, 0xed, 0xce, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 ed ce d9 12 \tvgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0xce, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 ce d9 12 \tvgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0xad, 0x40, 0xce, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 ad 40 ce d9 12 \tvgf2p8affineqb $0x12,%zmm25,%zmm26,%zmm27",}, +{{0x66, 0x0f, 0x3a, 0xcf, 0xd9, 0x12, }, 6, 0, "", "", +"66 0f 3a cf d9 12 \tgf2p8affineinvqb $0x12,%xmm1,%xmm3",}, +{{0xc4, 0xe3, 0xe9, 0xcf, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 e9 cf d9 12 \tvgf2p8affineinvqb $0x12,%xmm1,%xmm2,%xmm3",}, +{{0xc4, 0xe3, 0xed, 0xcf, 0xd9, 0x12, }, 6, 0, "", "", +"c4 e3 ed cf d9 12 \tvgf2p8affineinvqb $0x12,%ymm1,%ymm2,%ymm3",}, +{{0x62, 0xf3, 0xed, 0x48, 0xcf, 0xd9, 0x12, }, 7, 0, "", "", +"62 f3 ed 48 cf d9 12 \tvgf2p8affineinvqb $0x12,%zmm1,%zmm2,%zmm3",}, +{{0x62, 0x03, 0xad, 0x40, 0xcf, 0xd9, 0x12, }, 7, 0, "", "", +"62 03 ad 40 cf d9 12 \tvgf2p8affineinvqb $0x12,%zmm25,%zmm26,%zmm27",}, {{0x62, 0x91, 0x2d, 0x40, 0x72, 0xc1, 0x12, }, 7, 0, "", "", "62 91 2d 40 72 c1 12 \tvprord $0x12,%zmm25,%zmm26",}, {{0x62, 0x91, 0xad, 0x40, 0x72, 0xc1, 0x12, }, 7, 0, "", "", @@ -1667,6 +2151,16 @@ "41 0f ae 30 \txsaveopt (%r8)",}, {{0x0f, 0xae, 0xf0, }, 3, 0, "", "", "0f ae f0 \tmfence ",}, +{{0x0f, 0x1c, 0x00, }, 3, 0, "", "", +"0f 1c 00 \tcldemote (%rax)",}, +{{0x41, 0x0f, 0x1c, 0x00, }, 4, 0, "", "", +"41 0f 1c 00 \tcldemote (%r8)",}, +{{0x0f, 0x1c, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f 1c 04 25 78 56 34 12 \tcldemote 0x12345678",}, +{{0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%rax,%rcx,8)",}, +{{0x41, 0x0f, 0x1c, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"41 0f 1c 84 c8 78 56 34 12 \tcldemote 0x12345678(%r8,%rcx,8)",}, {{0x0f, 0xc7, 0x20, }, 3, 0, "", "", "0f c7 20 \txsavec (%rax)",}, {{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "", @@ -1727,3 +2221,55 @@ "f3 48 0f ae a4 c8 78 56 34 12 \tptwriteq 0x12345678(%rax,%rcx,8)",}, {{0xf3, 0x49, 0x0f, 0xae, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", "f3 49 0f ae a4 c8 78 56 34 12 \tptwriteq 0x12345678(%r8,%rcx,8)",}, +{{0x66, 0x0f, 0xae, 0xf3, }, 4, 0, "", "", +"66 0f ae f3 \ttpause %ebx",}, +{{0x66, 0x41, 0x0f, 0xae, 0xf0, }, 5, 0, "", "", +"66 41 0f ae f0 \ttpause %r8d",}, +{{0x67, 0xf3, 0x0f, 0xae, 0xf0, }, 5, 0, "", "", +"67 f3 0f ae f0 \tumonitor %eax",}, +{{0xf3, 0x0f, 0xae, 0xf0, }, 4, 0, "", "", +"f3 0f ae f0 \tumonitor %rax",}, +{{0x67, 0xf3, 0x41, 0x0f, 0xae, 0xf0, }, 6, 0, "", "", +"67 f3 41 0f ae f0 \tumonitor %r8d",}, +{{0xf2, 0x0f, 0xae, 0xf0, }, 4, 0, "", "", +"f2 0f ae f0 \tumwait %eax",}, +{{0xf2, 0x41, 0x0f, 0xae, 0xf0, }, 5, 0, "", "", +"f2 41 0f ae f0 \tumwait %r8d",}, +{{0x48, 0x0f, 0x38, 0xf9, 0x03, }, 5, 0, "", "", +"48 0f 38 f9 03 \tmovdiri %rax,(%rbx)",}, +{{0x48, 0x0f, 0x38, 0xf9, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"48 0f 38 f9 88 78 56 34 12 \tmovdiri %rcx,0x12345678(%rax)",}, +{{0x66, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "", +"66 0f 38 f8 18 \tmovdir64b (%rax),%rbx",}, +{{0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%rax),%rcx",}, +{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "", +"67 66 0f 38 f8 18 \tmovdir64b (%eax),%ebx",}, +{{0x67, 0x66, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"67 66 0f 38 f8 88 78 56 34 12 \tmovdir64b 0x12345678(%eax),%ecx",}, +{{0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "", +"f2 0f 38 f8 18 \tenqcmd (%rax),%rbx",}, +{{0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%rax),%rcx",}, +{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "", +"67 f2 0f 38 f8 18 \tenqcmd (%eax),%ebx",}, +{{0x67, 0xf2, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"67 f2 0f 38 f8 88 78 56 34 12 \tenqcmd 0x12345678(%eax),%ecx",}, +{{0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 5, 0, "", "", +"f3 0f 38 f8 18 \tenqcmds (%rax),%rbx",}, +{{0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%rax),%rcx",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x18, }, 6, 0, "", "", +"67 f3 0f 38 f8 18 \tenqcmds (%eax),%ebx",}, +{{0x67, 0xf3, 0x0f, 0x38, 0xf8, 0x88, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"67 f3 0f 38 f8 88 78 56 34 12 \tenqcmds 0x12345678(%eax),%ecx",}, +{{0x0f, 0x01, 0xcf, }, 3, 0, "", "", +"0f 01 cf \tencls ",}, +{{0x0f, 0x01, 0xd7, }, 3, 0, "", "", +"0f 01 d7 \tenclu ",}, +{{0x0f, 0x01, 0xc0, }, 3, 0, "", "", +"0f 01 c0 \tenclv ",}, +{{0x0f, 0x01, 0xc5, }, 3, 0, "", "", +"0f 01 c5 \tpconfig ",}, +{{0xf3, 0x0f, 0x09, }, 3, 0, "", "", +"f3 0f 09 \twbnoinvd ",}, diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c index 891415b10984..ddbf07c50bb8 100644 --- a/tools/perf/arch/x86/tests/insn-x86-dat-src.c +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c @@ -510,6 +510,82 @@ int main(void) asm volatile("vrsqrt14ss %xmm24,%xmm25,%xmm26{%k7}"); asm volatile("vrsqrt14sd %xmm24,%xmm25,%xmm26{%k7}"); + /* AVX-512: Op code 0f 38 50 */ + + asm volatile("vpdpbusd %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpbusd %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpbusd %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpbusd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 51 */ + + asm volatile("vpdpbusds %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpbusds %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpbusds %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpbusds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 52 */ + + asm volatile("vdpbf16ps %xmm1, %xmm2, %xmm3"); + asm volatile("vdpbf16ps %ymm1, %ymm2, %ymm3"); + asm volatile("vdpbf16ps %zmm1, %zmm2, %zmm3"); + asm volatile("vdpbf16ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vpdpwssd %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpwssd %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpwssd %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpwssd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vp4dpwssd (%rax), %zmm0, %zmm4"); + asm volatile("vp4dpwssd (%eax), %zmm0, %zmm4"); + asm volatile("vp4dpwssd 0x12345678(%rax,%rcx,8),%zmm0,%zmm4"); + asm volatile("vp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 53 */ + + asm volatile("vpdpwssds %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpwssds %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpwssds %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpwssds 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vp4dpwssds (%rax), %zmm0, %zmm4"); + asm volatile("vp4dpwssds (%eax), %zmm0, %zmm4"); + asm volatile("vp4dpwssds 0x12345678(%rax,%rcx,8),%zmm0,%zmm4"); + asm volatile("vp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 54 */ + + asm volatile("vpopcntb %xmm1, %xmm2"); + asm volatile("vpopcntb %ymm1, %ymm2"); + asm volatile("vpopcntb %zmm1, %zmm2"); + asm volatile("vpopcntb 0x12345678(%rax,%rcx,8),%zmm2"); + asm volatile("vpopcntb 0x12345678(%eax,%ecx,8),%zmm2"); + + asm volatile("vpopcntw %xmm1, %xmm2"); + asm volatile("vpopcntw %ymm1, %ymm2"); + asm volatile("vpopcntw %zmm1, %zmm2"); + asm volatile("vpopcntw 0x12345678(%rax,%rcx,8),%zmm2"); + asm volatile("vpopcntw 0x12345678(%eax,%ecx,8),%zmm2"); + + /* AVX-512: Op code 0f 38 55 */ + + asm volatile("vpopcntd %xmm1, %xmm2"); + asm volatile("vpopcntd %ymm1, %ymm2"); + asm volatile("vpopcntd %zmm1, %zmm2"); + asm volatile("vpopcntd 0x12345678(%rax,%rcx,8),%zmm2"); + asm volatile("vpopcntd 0x12345678(%eax,%ecx,8),%zmm2"); + + asm volatile("vpopcntq %xmm1, %xmm2"); + asm volatile("vpopcntq %ymm1, %ymm2"); + asm volatile("vpopcntq %zmm1, %zmm2"); + asm volatile("vpopcntq 0x12345678(%rax,%rcx,8),%zmm2"); + asm volatile("vpopcntq 0x12345678(%eax,%ecx,8),%zmm2"); + /* AVX-512: Op code 0f 38 59 */ asm volatile("vpbroadcastq %xmm4,%xmm6"); @@ -526,6 +602,34 @@ int main(void) asm volatile("vbroadcasti32x8 (%rcx),%zmm28"); asm volatile("vbroadcasti64x4 (%rcx),%zmm26"); + /* AVX-512: Op code 0f 38 62 */ + + asm volatile("vpexpandb %xmm1, %xmm2"); + asm volatile("vpexpandb %ymm1, %ymm2"); + asm volatile("vpexpandb %zmm1, %zmm2"); + asm volatile("vpexpandb 0x12345678(%rax,%rcx,8),%zmm2"); + asm volatile("vpexpandb 0x12345678(%eax,%ecx,8),%zmm2"); + + asm volatile("vpexpandw %xmm1, %xmm2"); + asm volatile("vpexpandw %ymm1, %ymm2"); + asm volatile("vpexpandw %zmm1, %zmm2"); + asm volatile("vpexpandw 0x12345678(%rax,%rcx,8),%zmm2"); + asm volatile("vpexpandw 0x12345678(%eax,%ecx,8),%zmm2"); + + /* AVX-512: Op code 0f 38 63 */ + + asm volatile("vpcompressb %xmm1, %xmm2"); + asm volatile("vpcompressb %ymm1, %ymm2"); + asm volatile("vpcompressb %zmm1, %zmm2"); + asm volatile("vpcompressb %zmm2,0x12345678(%rax,%rcx,8)"); + asm volatile("vpcompressb %zmm2,0x12345678(%eax,%ecx,8)"); + + asm volatile("vpcompressw %xmm1, %xmm2"); + asm volatile("vpcompressw %ymm1, %ymm2"); + asm volatile("vpcompressw %zmm1, %zmm2"); + asm volatile("vpcompressw %zmm2,0x12345678(%rax,%rcx,8)"); + asm volatile("vpcompressw %zmm2,0x12345678(%eax,%ecx,8)"); + /* AVX-512: Op code 0f 38 64 */ asm volatile("vpblendmd %zmm26,%zmm27,%zmm28"); @@ -541,6 +645,76 @@ int main(void) asm volatile("vpblendmb %zmm26,%zmm27,%zmm28"); asm volatile("vpblendmw %zmm26,%zmm27,%zmm28"); + /* AVX-512: Op code 0f 38 68 */ + + asm volatile("vp2intersectd %xmm1, %xmm2, %k3"); + asm volatile("vp2intersectd %ymm1, %ymm2, %k3"); + asm volatile("vp2intersectd %zmm1, %zmm2, %k3"); + asm volatile("vp2intersectd 0x12345678(%rax,%rcx,8),%zmm2,%k3"); + asm volatile("vp2intersectd 0x12345678(%eax,%ecx,8),%zmm2,%k3"); + + asm volatile("vp2intersectq %xmm1, %xmm2, %k3"); + asm volatile("vp2intersectq %ymm1, %ymm2, %k3"); + asm volatile("vp2intersectq %zmm1, %zmm2, %k3"); + asm volatile("vp2intersectq 0x12345678(%rax,%rcx,8),%zmm2,%k3"); + asm volatile("vp2intersectq 0x12345678(%eax,%ecx,8),%zmm2,%k3"); + + /* AVX-512: Op code 0f 38 70 */ + + asm volatile("vpshldvw %xmm1, %xmm2, %xmm3"); + asm volatile("vpshldvw %ymm1, %ymm2, %ymm3"); + asm volatile("vpshldvw %zmm1, %zmm2, %zmm3"); + asm volatile("vpshldvw 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpshldvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 71 */ + + asm volatile("vpshldvd %xmm1, %xmm2, %xmm3"); + asm volatile("vpshldvd %ymm1, %ymm2, %ymm3"); + asm volatile("vpshldvd %zmm1, %zmm2, %zmm3"); + asm volatile("vpshldvd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpshldvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vpshldvq %xmm1, %xmm2, %xmm3"); + asm volatile("vpshldvq %ymm1, %ymm2, %ymm3"); + asm volatile("vpshldvq %zmm1, %zmm2, %zmm3"); + asm volatile("vpshldvq 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpshldvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 72 */ + + asm volatile("vcvtne2ps2bf16 %xmm1, %xmm2, %xmm3"); + asm volatile("vcvtne2ps2bf16 %ymm1, %ymm2, %ymm3"); + asm volatile("vcvtne2ps2bf16 %zmm1, %zmm2, %zmm3"); + asm volatile("vcvtne2ps2bf16 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vcvtne2ps2bf16 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vcvtneps2bf16 %xmm1, %xmm2"); + asm volatile("vcvtneps2bf16 %ymm1, %xmm2"); + asm volatile("vcvtneps2bf16 %zmm1, %ymm2"); + asm volatile("vcvtneps2bf16 0x12345678(%rax,%rcx,8),%ymm2"); + asm volatile("vcvtneps2bf16 0x12345678(%eax,%ecx,8),%ymm2"); + + asm volatile("vpshrdvw %xmm1, %xmm2, %xmm3"); + asm volatile("vpshrdvw %ymm1, %ymm2, %ymm3"); + asm volatile("vpshrdvw %zmm1, %zmm2, %zmm3"); + asm volatile("vpshrdvw 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpshrdvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 73 */ + + asm volatile("vpshrdvd %xmm1, %xmm2, %xmm3"); + asm volatile("vpshrdvd %ymm1, %ymm2, %ymm3"); + asm volatile("vpshrdvd %zmm1, %zmm2, %zmm3"); + asm volatile("vpshrdvd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vpshrdvq %xmm1, %xmm2, %xmm3"); + asm volatile("vpshrdvq %ymm1, %ymm2, %ymm3"); + asm volatile("vpshrdvq %zmm1, %zmm2, %zmm3"); + asm volatile("vpshrdvq 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + /* AVX-512: Op code 0f 38 75 */ asm volatile("vpermi2b %zmm24,%zmm25,%zmm26"); @@ -613,6 +787,14 @@ int main(void) asm volatile("vpermb %zmm26,%zmm27,%zmm28"); asm volatile("vpermw %zmm26,%zmm27,%zmm28"); + /* AVX-512: Op code 0f 38 8f */ + + asm volatile("vpshufbitqmb %xmm1, %xmm2, %k3"); + asm volatile("vpshufbitqmb %ymm1, %ymm2, %k3"); + asm volatile("vpshufbitqmb %zmm1, %zmm2, %k3"); + asm volatile("vpshufbitqmb 0x12345678(%rax,%rcx,8),%zmm2,%k3"); + asm volatile("vpshufbitqmb 0x12345678(%eax,%ecx,8),%zmm2,%k3"); + /* AVX-512: Op code 0f 38 90 */ asm volatile("vpgatherdd %xmm2,0x02(%rbp,%xmm7,2),%xmm1"); @@ -627,6 +809,40 @@ int main(void) asm volatile("vpgatherqd 0x7b(%rbp,%zmm27,8),%ymm26{%k1}"); asm volatile("vpgatherqq 0x7b(%rbp,%zmm27,8),%zmm26{%k1}"); + /* AVX-512: Op code 0f 38 9a */ + + asm volatile("vfmsub132ps %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132ps %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub132ps %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub132ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vfmsub132ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vfmsub132pd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132pd %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub132pd %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub132pd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vfmsub132pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("v4fmaddps (%rax), %zmm0, %zmm4"); + asm volatile("v4fmaddps (%eax), %zmm0, %zmm4"); + asm volatile("v4fmaddps 0x12345678(%rax,%rcx,8),%zmm0,%zmm4"); + asm volatile("v4fmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 9b */ + + asm volatile("vfmsub132ss %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132ss 0x12345678(%rax,%rcx,8),%xmm2,%xmm3"); + asm volatile("vfmsub132ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("vfmsub132sd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132sd 0x12345678(%rax,%rcx,8),%xmm2,%xmm3"); + asm volatile("vfmsub132sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("v4fmaddss (%rax), %xmm0, %xmm4"); + asm volatile("v4fmaddss (%eax), %xmm0, %xmm4"); + asm volatile("v4fmaddss 0x12345678(%rax,%rcx,8),%xmm0,%xmm4"); + asm volatile("v4fmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4"); + /* AVX-512: Op code 0f 38 a0 */ asm volatile("vpscatterdd %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); @@ -647,6 +863,40 @@ int main(void) asm volatile("vscatterqps %ymm6,0x7b(%rbp,%zmm29,8){%k1}"); asm volatile("vscatterqpd %zmm28,0x7b(%rbp,%zmm29,8){%k1}"); + /* AVX-512: Op code 0f 38 aa */ + + asm volatile("vfmsub213ps %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213ps %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub213ps %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub213ps 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vfmsub213ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vfmsub213pd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213pd %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub213pd %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub213pd 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vfmsub213pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("v4fnmaddps (%rax), %zmm0, %zmm4"); + asm volatile("v4fnmaddps (%eax), %zmm0, %zmm4"); + asm volatile("v4fnmaddps 0x12345678(%rax,%rcx,8),%zmm0,%zmm4"); + asm volatile("v4fnmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 ab */ + + asm volatile("vfmsub213ss %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213ss 0x12345678(%rax,%rcx,8),%xmm2,%xmm3"); + asm volatile("vfmsub213ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("vfmsub213sd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213sd 0x12345678(%rax,%rcx,8),%xmm2,%xmm3"); + asm volatile("vfmsub213sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("v4fnmaddss (%rax), %xmm0, %xmm4"); + asm volatile("v4fnmaddss (%eax), %xmm0, %xmm4"); + asm volatile("v4fnmaddss 0x12345678(%rax,%rcx,8),%xmm0,%xmm4"); + asm volatile("v4fnmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4"); + /* AVX-512: Op code 0f 38 b4 */ asm volatile("vpmadd52luq %zmm26,%zmm27,%zmm28"); @@ -685,6 +935,50 @@ int main(void) asm volatile("vrsqrt28ss %xmm28,%xmm29,%xmm30{%k7}"); asm volatile("vrsqrt28sd %xmm25,%xmm26,%xmm27{%k7}"); + /* AVX-512: Op code 0f 38 cf */ + + asm volatile("gf2p8mulb %xmm1, %xmm3"); + asm volatile("gf2p8mulb 0x12345678(%rax,%rcx,8),%xmm3"); + asm volatile("gf2p8mulb 0x12345678(%eax,%ecx,8),%xmm3"); + + asm volatile("vgf2p8mulb %xmm1, %xmm2, %xmm3"); + asm volatile("vgf2p8mulb %ymm1, %ymm2, %ymm3"); + asm volatile("vgf2p8mulb %zmm1, %zmm2, %zmm3"); + asm volatile("vgf2p8mulb 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vgf2p8mulb 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 dc */ + + asm volatile("vaesenc %xmm1, %xmm2, %xmm3"); + asm volatile("vaesenc %ymm1, %ymm2, %ymm3"); + asm volatile("vaesenc %zmm1, %zmm2, %zmm3"); + asm volatile("vaesenc 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vaesenc 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 dd */ + + asm volatile("vaesenclast %xmm1, %xmm2, %xmm3"); + asm volatile("vaesenclast %ymm1, %ymm2, %ymm3"); + asm volatile("vaesenclast %zmm1, %zmm2, %zmm3"); + asm volatile("vaesenclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 de */ + + asm volatile("vaesdec %xmm1, %xmm2, %xmm3"); + asm volatile("vaesdec %ymm1, %ymm2, %ymm3"); + asm volatile("vaesdec %zmm1, %zmm2, %zmm3"); + asm volatile("vaesdec 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 df */ + + asm volatile("vaesdeclast %xmm1, %xmm2, %xmm3"); + asm volatile("vaesdeclast %ymm1, %ymm2, %ymm3"); + asm volatile("vaesdeclast %zmm1, %zmm2, %zmm3"); + asm volatile("vaesdeclast 0x12345678(%rax,%rcx,8),%zmm2,%zmm3"); + asm volatile("vaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + /* AVX-512: Op code 0f 3a 03 */ asm volatile("valignd $0x12,%zmm28,%zmm29,%zmm30"); @@ -804,6 +1098,13 @@ int main(void) asm volatile("vshufi32x4 $0x12,%zmm25,%zmm26,%zmm27"); asm volatile("vshufi64x2 $0x12,%zmm28,%zmm29,%zmm30"); + /* AVX-512: Op code 0f 3a 44 */ + + asm volatile("vpclmulqdq $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpclmulqdq $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpclmulqdq $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vpclmulqdq $0x12,%zmm25,%zmm26,%zmm27"); + /* AVX-512: Op code 0f 3a 50 */ asm volatile("vrangeps $0x12,%zmm25,%zmm26,%zmm27"); @@ -844,6 +1145,62 @@ int main(void) asm volatile("vfpclassss $0x12,%xmm27,%k5"); asm volatile("vfpclasssd $0x12,%xmm30,%k5"); + /* AVX-512: Op code 0f 3a 70 */ + + asm volatile("vpshldw $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshldw $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshldw $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vpshldw $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 71 */ + + asm volatile("vpshldd $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshldd $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshldd $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vpshldd $0x12,%zmm25,%zmm26,%zmm27"); + + asm volatile("vpshldq $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshldq $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshldq $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vpshldq $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 72 */ + + asm volatile("vpshrdw $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshrdw $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshrdw $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vpshrdw $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a 73 */ + + asm volatile("vpshrdd $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshrdd $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshrdd $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vpshrdd $0x12,%zmm25,%zmm26,%zmm27"); + + asm volatile("vpshrdq $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshrdq $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshrdq $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vpshrdq $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a ce */ + + asm volatile("gf2p8affineqb $0x12,%xmm1,%xmm3"); + + asm volatile("vgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vgf2p8affineqb $0x12,%zmm25,%zmm26,%zmm27"); + + /* AVX-512: Op code 0f 3a cf */ + + asm volatile("gf2p8affineinvqb $0x12,%xmm1,%xmm3"); + + asm volatile("vgf2p8affineinvqb $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vgf2p8affineinvqb $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vgf2p8affineinvqb $0x12,%zmm1,%zmm2,%zmm3"); + asm volatile("vgf2p8affineinvqb $0x12,%zmm25,%zmm26,%zmm27"); + /* AVX-512: Op code 0f 72 (Grp13) */ asm volatile("vprord $0x12,%zmm25,%zmm26"); @@ -1320,6 +1677,14 @@ int main(void) asm volatile("xsaveopt (%r8)"); asm volatile("mfence"); + /* cldemote m8 */ + + asm volatile("cldemote (%rax)"); + asm volatile("cldemote (%r8)"); + asm volatile("cldemote (0x12345678)"); + asm volatile("cldemote 0x12345678(%rax,%rcx,8)"); + asm volatile("cldemote 0x12345678(%r8,%rcx,8)"); + /* xsavec mem */ asm volatile("xsavec (%rax)"); @@ -1364,6 +1729,48 @@ int main(void) asm volatile("ptwriteq 0x12345678(%rax,%rcx,8)"); asm volatile("ptwriteq 0x12345678(%r8,%rcx,8)"); + /* tpause */ + + asm volatile("tpause %ebx"); + asm volatile("tpause %r8d"); + + /* umonitor */ + + asm volatile("umonitor %eax"); + asm volatile("umonitor %rax"); + asm volatile("umonitor %r8d"); + + /* umwait */ + + asm volatile("umwait %eax"); + asm volatile("umwait %r8d"); + + /* movdiri */ + + asm volatile("movdiri %rax,(%rbx)"); + asm volatile("movdiri %rcx,0x12345678(%rax)"); + + /* movdir64b */ + + asm volatile("movdir64b (%rax),%rbx"); + asm volatile("movdir64b 0x12345678(%rax),%rcx"); + asm volatile("movdir64b (%eax),%ebx"); + asm volatile("movdir64b 0x12345678(%eax),%ecx"); + + /* enqcmd */ + + asm volatile("enqcmd (%rax),%rbx"); + asm volatile("enqcmd 0x12345678(%rax),%rcx"); + asm volatile("enqcmd (%eax),%ebx"); + asm volatile("enqcmd 0x12345678(%eax),%ecx"); + + /* enqcmds */ + + asm volatile("enqcmds (%rax),%rbx"); + asm volatile("enqcmds 0x12345678(%rax),%rcx"); + asm volatile("enqcmds (%eax),%ebx"); + asm volatile("enqcmds 0x12345678(%eax),%ecx"); + #else /* #ifdef __x86_64__ */ /* bound r32, mem (same op code as EVEX prefix) */ @@ -1896,6 +2303,69 @@ int main(void) asm volatile("vrsqrt14ss %xmm4,%xmm5,%xmm6{%k7}"); asm volatile("vrsqrt14sd %xmm4,%xmm5,%xmm6{%k7}"); + /* AVX-512: Op code 0f 38 50 */ + + asm volatile("vpdpbusd %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpbusd %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpbusd %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpbusd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 51 */ + + asm volatile("vpdpbusds %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpbusds %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpbusds %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpbusds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 52 */ + + asm volatile("vdpbf16ps %xmm1, %xmm2, %xmm3"); + asm volatile("vdpbf16ps %ymm1, %ymm2, %ymm3"); + asm volatile("vdpbf16ps %zmm1, %zmm2, %zmm3"); + asm volatile("vdpbf16ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vpdpwssd %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpwssd %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpwssd %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpwssd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vp4dpwssd (%eax), %zmm0, %zmm4"); + asm volatile("vp4dpwssd 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 53 */ + + asm volatile("vpdpwssds %xmm1, %xmm2, %xmm3"); + asm volatile("vpdpwssds %ymm1, %ymm2, %ymm3"); + asm volatile("vpdpwssds %zmm1, %zmm2, %zmm3"); + asm volatile("vpdpwssds 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vp4dpwssds (%eax), %zmm0, %zmm4"); + asm volatile("vp4dpwssds 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 54 */ + + asm volatile("vpopcntb %xmm1, %xmm2"); + asm volatile("vpopcntb %ymm1, %ymm2"); + asm volatile("vpopcntb %zmm1, %zmm2"); + asm volatile("vpopcntb 0x12345678(%eax,%ecx,8),%zmm2"); + + asm volatile("vpopcntw %xmm1, %xmm2"); + asm volatile("vpopcntw %ymm1, %ymm2"); + asm volatile("vpopcntw %zmm1, %zmm2"); + asm volatile("vpopcntw 0x12345678(%eax,%ecx,8),%zmm2"); + + /* AVX-512: Op code 0f 38 55 */ + + asm volatile("vpopcntd %xmm1, %xmm2"); + asm volatile("vpopcntd %ymm1, %ymm2"); + asm volatile("vpopcntd %zmm1, %zmm2"); + asm volatile("vpopcntd 0x12345678(%eax,%ecx,8),%zmm2"); + + asm volatile("vpopcntq %xmm1, %xmm2"); + asm volatile("vpopcntq %ymm1, %ymm2"); + asm volatile("vpopcntq %zmm1, %zmm2"); + asm volatile("vpopcntq 0x12345678(%eax,%ecx,8),%zmm2"); + /* AVX-512: Op code 0f 38 59 */ asm volatile("vpbroadcastq %xmm4,%xmm6"); @@ -1912,6 +2382,30 @@ int main(void) asm volatile("vbroadcasti32x8 (%ecx),%zmm6"); asm volatile("vbroadcasti64x4 (%ecx),%zmm6"); + /* AVX-512: Op code 0f 38 62 */ + + asm volatile("vpexpandb %xmm1, %xmm2"); + asm volatile("vpexpandb %ymm1, %ymm2"); + asm volatile("vpexpandb %zmm1, %zmm2"); + asm volatile("vpexpandb 0x12345678(%eax,%ecx,8),%zmm2"); + + asm volatile("vpexpandw %xmm1, %xmm2"); + asm volatile("vpexpandw %ymm1, %ymm2"); + asm volatile("vpexpandw %zmm1, %zmm2"); + asm volatile("vpexpandw 0x12345678(%eax,%ecx,8),%zmm2"); + + /* AVX-512: Op code 0f 38 63 */ + + asm volatile("vpcompressb %xmm1, %xmm2"); + asm volatile("vpcompressb %ymm1, %ymm2"); + asm volatile("vpcompressb %zmm1, %zmm2"); + asm volatile("vpcompressb %zmm2,0x12345678(%eax,%ecx,8)"); + + asm volatile("vpcompressw %xmm1, %xmm2"); + asm volatile("vpcompressw %ymm1, %ymm2"); + asm volatile("vpcompressw %zmm1, %zmm2"); + asm volatile("vpcompressw %zmm2,0x12345678(%eax,%ecx,8)"); + /* AVX-512: Op code 0f 38 64 */ asm volatile("vpblendmd %zmm4,%zmm5,%zmm6"); @@ -1927,6 +2421,66 @@ int main(void) asm volatile("vpblendmb %zmm4,%zmm5,%zmm6"); asm volatile("vpblendmw %zmm4,%zmm5,%zmm6"); + /* AVX-512: Op code 0f 38 68 */ + + asm volatile("vp2intersectd %xmm1, %xmm2, %k3"); + asm volatile("vp2intersectd %ymm1, %ymm2, %k3"); + asm volatile("vp2intersectd %zmm1, %zmm2, %k3"); + asm volatile("vp2intersectd 0x12345678(%eax,%ecx,8),%zmm2,%k3"); + + asm volatile("vp2intersectq %xmm1, %xmm2, %k3"); + asm volatile("vp2intersectq %ymm1, %ymm2, %k3"); + asm volatile("vp2intersectq %zmm1, %zmm2, %k3"); + asm volatile("vp2intersectq 0x12345678(%eax,%ecx,8),%zmm2,%k3"); + + /* AVX-512: Op code 0f 38 70 */ + + asm volatile("vpshldvw %xmm1, %xmm2, %xmm3"); + asm volatile("vpshldvw %ymm1, %ymm2, %ymm3"); + asm volatile("vpshldvw %zmm1, %zmm2, %zmm3"); + asm volatile("vpshldvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 71 */ + + asm volatile("vpshldvd %xmm1, %xmm2, %xmm3"); + asm volatile("vpshldvd %ymm1, %ymm2, %ymm3"); + asm volatile("vpshldvd %zmm1, %zmm2, %zmm3"); + asm volatile("vpshldvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vpshldvq %xmm1, %xmm2, %xmm3"); + asm volatile("vpshldvq %ymm1, %ymm2, %ymm3"); + asm volatile("vpshldvq %zmm1, %zmm2, %zmm3"); + asm volatile("vpshldvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 72 */ + + asm volatile("vcvtne2ps2bf16 %xmm1, %xmm2, %xmm3"); + asm volatile("vcvtne2ps2bf16 %ymm1, %ymm2, %ymm3"); + asm volatile("vcvtne2ps2bf16 %zmm1, %zmm2, %zmm3"); + asm volatile("vcvtne2ps2bf16 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vcvtneps2bf16 %xmm1, %xmm2"); + asm volatile("vcvtneps2bf16 %ymm1, %xmm2"); + asm volatile("vcvtneps2bf16 %zmm1, %ymm2"); + asm volatile("vcvtneps2bf16 0x12345678(%eax,%ecx,8),%ymm2"); + + asm volatile("vpshrdvw %xmm1, %xmm2, %xmm3"); + asm volatile("vpshrdvw %ymm1, %ymm2, %ymm3"); + asm volatile("vpshrdvw %zmm1, %zmm2, %zmm3"); + asm volatile("vpshrdvw 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 73 */ + + asm volatile("vpshrdvd %xmm1, %xmm2, %xmm3"); + asm volatile("vpshrdvd %ymm1, %ymm2, %ymm3"); + asm volatile("vpshrdvd %zmm1, %zmm2, %zmm3"); + asm volatile("vpshrdvd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vpshrdvq %xmm1, %xmm2, %xmm3"); + asm volatile("vpshrdvq %ymm1, %ymm2, %ymm3"); + asm volatile("vpshrdvq %zmm1, %zmm2, %zmm3"); + asm volatile("vpshrdvq 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + /* AVX-512: Op code 0f 38 75 */ asm volatile("vpermi2b %zmm4,%zmm5,%zmm6"); @@ -1998,6 +2552,13 @@ int main(void) asm volatile("vpermb %zmm4,%zmm5,%zmm6"); asm volatile("vpermw %zmm4,%zmm5,%zmm6"); + /* AVX-512: Op code 0f 38 8f */ + + asm volatile("vpshufbitqmb %xmm1, %xmm2, %k3"); + asm volatile("vpshufbitqmb %ymm1, %ymm2, %k3"); + asm volatile("vpshufbitqmb %zmm1, %zmm2, %k3"); + asm volatile("vpshufbitqmb 0x12345678(%eax,%ecx,8),%zmm2,%k3"); + /* AVX-512: Op code 0f 38 90 */ asm volatile("vpgatherdd %xmm2,0x02(%ebp,%xmm7,2),%xmm1"); @@ -2012,6 +2573,32 @@ int main(void) asm volatile("vpgatherqd 0x7b(%ebp,%zmm7,8),%ymm6{%k1}"); asm volatile("vpgatherqq 0x7b(%ebp,%zmm7,8),%zmm6{%k1}"); + /* AVX-512: Op code 0f 38 9a */ + + asm volatile("vfmsub132ps %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132ps %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub132ps %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub132ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vfmsub132pd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132pd %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub132pd %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub132pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("v4fmaddps (%eax), %zmm0, %zmm4"); + asm volatile("v4fmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 9b */ + + asm volatile("vfmsub132ss %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("vfmsub132sd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub132sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("v4fmaddss (%eax), %xmm0, %xmm4"); + asm volatile("v4fmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4"); + /* AVX-512: Op code 0f 38 a0 */ asm volatile("vpscatterdd %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); @@ -2032,6 +2619,32 @@ int main(void) asm volatile("vscatterqps %ymm6,0x7b(%ebp,%zmm7,8){%k1}"); asm volatile("vscatterqpd %zmm6,0x7b(%ebp,%zmm7,8){%k1}"); + /* AVX-512: Op code 0f 38 aa */ + + asm volatile("vfmsub213ps %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213ps %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub213ps %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub213ps 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("vfmsub213pd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213pd %ymm1, %ymm2, %ymm3"); + asm volatile("vfmsub213pd %zmm1, %zmm2, %zmm3"); + asm volatile("vfmsub213pd 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + asm volatile("v4fnmaddps (%eax), %zmm0, %zmm4"); + asm volatile("v4fnmaddps 0x12345678(%eax,%ecx,8),%zmm0,%zmm4"); + + /* AVX-512: Op code 0f 38 ab */ + + asm volatile("vfmsub213ss %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213ss 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("vfmsub213sd %xmm1, %xmm2, %xmm3"); + asm volatile("vfmsub213sd 0x12345678(%eax,%ecx,8),%xmm2,%xmm3"); + + asm volatile("v4fnmaddss (%eax), %xmm0, %xmm4"); + asm volatile("v4fnmaddss 0x12345678(%eax,%ecx,8),%xmm0,%xmm4"); + /* AVX-512: Op code 0f 38 b4 */ asm volatile("vpmadd52luq %zmm4,%zmm5,%zmm6"); @@ -2070,6 +2683,44 @@ int main(void) asm volatile("vrsqrt28ss %xmm5,%xmm6,%xmm7{%k7}"); asm volatile("vrsqrt28sd %xmm5,%xmm6,%xmm7{%k7}"); + /* AVX-512: Op code 0f 38 cf */ + + asm volatile("gf2p8mulb %xmm1, %xmm3"); + asm volatile("gf2p8mulb 0x12345678(%eax,%ecx,8),%xmm3"); + + asm volatile("vgf2p8mulb %xmm1, %xmm2, %xmm3"); + asm volatile("vgf2p8mulb %ymm1, %ymm2, %ymm3"); + asm volatile("vgf2p8mulb %zmm1, %zmm2, %zmm3"); + asm volatile("vgf2p8mulb 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 dc */ + + asm volatile("vaesenc %xmm1, %xmm2, %xmm3"); + asm volatile("vaesenc %ymm1, %ymm2, %ymm3"); + asm volatile("vaesenc %zmm1, %zmm2, %zmm3"); + asm volatile("vaesenc 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 dd */ + + asm volatile("vaesenclast %xmm1, %xmm2, %xmm3"); + asm volatile("vaesenclast %ymm1, %ymm2, %ymm3"); + asm volatile("vaesenclast %zmm1, %zmm2, %zmm3"); + asm volatile("vaesenclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 de */ + + asm volatile("vaesdec %xmm1, %xmm2, %xmm3"); + asm volatile("vaesdec %ymm1, %ymm2, %ymm3"); + asm volatile("vaesdec %zmm1, %zmm2, %zmm3"); + asm volatile("vaesdec 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 38 df */ + + asm volatile("vaesdeclast %xmm1, %xmm2, %xmm3"); + asm volatile("vaesdeclast %ymm1, %ymm2, %ymm3"); + asm volatile("vaesdeclast %zmm1, %zmm2, %zmm3"); + asm volatile("vaesdeclast 0x12345678(%eax,%ecx,8),%zmm2,%zmm3"); + /* AVX-512: Op code 0f 3a 03 */ asm volatile("valignd $0x12,%zmm5,%zmm6,%zmm7"); @@ -2189,6 +2840,12 @@ int main(void) asm volatile("vshufi32x4 $0x12,%zmm5,%zmm6,%zmm7"); asm volatile("vshufi64x2 $0x12,%zmm5,%zmm6,%zmm7"); + /* AVX-512: Op code 0f 3a 44 */ + + asm volatile("vpclmulqdq $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpclmulqdq $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpclmulqdq $0x12,%zmm1,%zmm2,%zmm3"); + /* AVX-512: Op code 0f 3a 50 */ asm volatile("vrangeps $0x12,%zmm5,%zmm6,%zmm7"); @@ -2229,6 +2886,54 @@ int main(void) asm volatile("vfpclassss $0x12,%xmm7,%k5"); asm volatile("vfpclasssd $0x12,%xmm7,%k5"); + /* AVX-512: Op code 0f 3a 70 */ + + asm volatile("vpshldw $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshldw $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshldw $0x12,%zmm1,%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 3a 71 */ + + asm volatile("vpshldd $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshldd $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshldd $0x12,%zmm1,%zmm2,%zmm3"); + + asm volatile("vpshldq $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshldq $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshldq $0x12,%zmm1,%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 3a 72 */ + + asm volatile("vpshrdw $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshrdw $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshrdw $0x12,%zmm1,%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 3a 73 */ + + asm volatile("vpshrdd $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshrdd $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshrdd $0x12,%zmm1,%zmm2,%zmm3"); + + asm volatile("vpshrdq $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vpshrdq $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vpshrdq $0x12,%zmm1,%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 3a ce */ + + asm volatile("gf2p8affineqb $0x12,%xmm1,%xmm3"); + + asm volatile("vgf2p8affineqb $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vgf2p8affineqb $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vgf2p8affineqb $0x12,%zmm1,%zmm2,%zmm3"); + + /* AVX-512: Op code 0f 3a cf */ + + asm volatile("gf2p8affineinvqb $0x12,%xmm1,%xmm3"); + + asm volatile("vgf2p8affineinvqb $0x12,%xmm1,%xmm2,%xmm3"); + asm volatile("vgf2p8affineinvqb $0x12,%ymm1,%ymm2,%ymm3"); + asm volatile("vgf2p8affineinvqb $0x12,%zmm1,%zmm2,%zmm3"); + /* AVX-512: Op code 0f 72 (Grp13) */ asm volatile("vprord $0x12,%zmm5,%zmm6"); @@ -2656,6 +3361,12 @@ int main(void) asm volatile("xsaveopt (%eax)"); asm volatile("mfence"); + /* cldemote m8 */ + + asm volatile("cldemote (%eax)"); + asm volatile("cldemote (0x12345678)"); + asm volatile("cldemote 0x12345678(%eax,%ecx,8)"); + /* xsavec mem */ asm volatile("xsavec (%eax)"); @@ -2684,8 +3395,61 @@ int main(void) asm volatile("ptwritel (0x12345678)"); asm volatile("ptwritel 0x12345678(%eax,%ecx,8)"); + /* tpause */ + + asm volatile("tpause %ebx"); + + /* umonitor */ + + asm volatile("umonitor %ax"); + asm volatile("umonitor %eax"); + + /* umwait */ + + asm volatile("umwait %eax"); + + /* movdiri */ + + asm volatile("movdiri %eax,(%ebx)"); + asm volatile("movdiri %ecx,0x12345678(%eax)"); + + /* movdir64b */ + + asm volatile("movdir64b (%eax),%ebx"); + asm volatile("movdir64b 0x12345678(%eax),%ecx"); + asm volatile("movdir64b (%si),%bx"); + asm volatile("movdir64b 0x1234(%si),%cx"); + + /* enqcmd */ + + asm volatile("enqcmd (%eax),%ebx"); + asm volatile("enqcmd 0x12345678(%eax),%ecx"); + asm volatile("enqcmd (%si),%bx"); + asm volatile("enqcmd 0x1234(%si),%cx"); + + /* enqcmds */ + + asm volatile("enqcmds (%eax),%ebx"); + asm volatile("enqcmds 0x12345678(%eax),%ecx"); + asm volatile("enqcmds (%si),%bx"); + asm volatile("enqcmds 0x1234(%si),%cx"); + #endif /* #ifndef __x86_64__ */ + /* SGX */ + + asm volatile("encls"); + asm volatile("enclu"); + asm volatile("enclv"); + + /* pconfig */ + + asm volatile("pconfig"); + + /* wbnoinvd */ + + asm volatile("wbnoinvd"); + /* Following line is a marker for the awk script - do not change */ asm volatile("rdtsc"); /* Stop here */ diff --git a/tools/perf/arch/x86/tests/insn-x86.c b/tools/perf/arch/x86/tests/insn-x86.c index c3e5f4ab0d3e..745f29adb14b 100644 --- a/tools/perf/arch/x86/tests/insn-x86.c +++ b/tools/perf/arch/x86/tests/insn-x86.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 #include <linux/types.h> +#include "../../../../arch/x86/include/asm/insn.h" +#include <string.h> #include "debug.h" #include "tests/tests.h" #include "arch-tests.h" -#include "intel-pt-decoder/insn.h" #include "intel-pt-decoder/intel-pt-insn-decoder.h" struct test_data { diff --git a/tools/perf/arch/x86/tests/intel-cqm.c b/tools/perf/arch/x86/tests/intel-cqm.c index 90a4a8c58a62..3ec562a2aaba 100644 --- a/tools/perf/arch/x86/tests/intel-cqm.c +++ b/tools/perf/arch/x86/tests/intel-cqm.c @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 #include "tests/tests.h" -#include "perf.h" #include "cloexec.h" #include "debug.h" #include "evlist.h" #include "evsel.h" #include "arch-tests.h" +#include <internal/lib.h> // page_size #include <signal.h> #include <sys/mman.h> @@ -39,8 +39,8 @@ static pid_t spawn(void) */ int test__intel_cqm_count_nmi_context(struct test *test __maybe_unused, int subtest __maybe_unused) { - struct perf_evlist *evlist = NULL; - struct perf_evsel *evsel = NULL; + struct evlist *evlist = NULL; + struct evsel *evsel = NULL; struct perf_event_attr pe; int i, fd[2], flag, ret; size_t mmap_len; @@ -50,7 +50,7 @@ int test__intel_cqm_count_nmi_context(struct test *test __maybe_unused, int subt flag = perf_event_open_cloexec_flag(); - evlist = perf_evlist__new(); + evlist = evlist__new(); if (!evlist) { pr_debug("perf_evlist__new failed\n"); return TEST_FAIL; @@ -63,9 +63,9 @@ int test__intel_cqm_count_nmi_context(struct test *test __maybe_unused, int subt goto out; } - evsel = perf_evlist__first(evlist); + evsel = evlist__first(evlist); if (!evsel) { - pr_debug("perf_evlist__first failed\n"); + pr_debug("evlist__first failed\n"); goto out; } @@ -123,6 +123,6 @@ int test__intel_cqm_count_nmi_context(struct test *test __maybe_unused, int subt kill(pid, SIGKILL); wait(NULL); out: - perf_evlist__delete(evlist); + evlist__delete(evlist); return err; } diff --git a/tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c b/tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c new file mode 100644 index 000000000000..901bf1f449c4 --- /dev/null +++ b/tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <string.h> + +#include "intel-pt-decoder/intel-pt-pkt-decoder.h" + +#include "debug.h" +#include "tests/tests.h" +#include "arch-tests.h" + +/** + * struct test_data - Test data. + * @len: number of bytes to decode + * @bytes: bytes to decode + * @ctx: packet context to decode + * @packet: expected packet + * @new_ctx: expected new packet context + * @ctx_unchanged: the packet context must not change + */ +struct test_data { + int len; + u8 bytes[INTEL_PT_PKT_MAX_SZ]; + enum intel_pt_pkt_ctx ctx; + struct intel_pt_pkt packet; + enum intel_pt_pkt_ctx new_ctx; + int ctx_unchanged; +} data[] = { + /* Padding Packet */ + {1, {0}, 0, {INTEL_PT_PAD, 0, 0}, 0, 1 }, + /* Short Taken/Not Taken Packet */ + {1, {4}, 0, {INTEL_PT_TNT, 1, 0}, 0, 0 }, + {1, {6}, 0, {INTEL_PT_TNT, 1, 0x20ULL << 58}, 0, 0 }, + {1, {0x80}, 0, {INTEL_PT_TNT, 6, 0}, 0, 0 }, + {1, {0xfe}, 0, {INTEL_PT_TNT, 6, 0x3fULL << 58}, 0, 0 }, + /* Long Taken/Not Taken Packet */ + {8, {0x02, 0xa3, 2}, 0, {INTEL_PT_TNT, 1, 0xa302ULL << 47}, 0, 0 }, + {8, {0x02, 0xa3, 3}, 0, {INTEL_PT_TNT, 1, 0x1a302ULL << 47}, 0, 0 }, + {8, {0x02, 0xa3, 0, 0, 0, 0, 0, 0x80}, 0, {INTEL_PT_TNT, 47, 0xa302ULL << 1}, 0, 0 }, + {8, {0x02, 0xa3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}, 0, {INTEL_PT_TNT, 47, 0xffffffffffffa302ULL << 1}, 0, 0 }, + /* Target IP Packet */ + {1, {0x0d}, 0, {INTEL_PT_TIP, 0, 0}, 0, 0 }, + {3, {0x2d, 1, 2}, 0, {INTEL_PT_TIP, 1, 0x201}, 0, 0 }, + {5, {0x4d, 1, 2, 3, 4}, 0, {INTEL_PT_TIP, 2, 0x4030201}, 0, 0 }, + {7, {0x6d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP, 3, 0x60504030201}, 0, 0 }, + {7, {0x8d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP, 4, 0x60504030201}, 0, 0 }, + {9, {0xcd, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP, 6, 0x807060504030201}, 0, 0 }, + /* Packet Generation Enable */ + {1, {0x11}, 0, {INTEL_PT_TIP_PGE, 0, 0}, 0, 0 }, + {3, {0x31, 1, 2}, 0, {INTEL_PT_TIP_PGE, 1, 0x201}, 0, 0 }, + {5, {0x51, 1, 2, 3, 4}, 0, {INTEL_PT_TIP_PGE, 2, 0x4030201}, 0, 0 }, + {7, {0x71, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGE, 3, 0x60504030201}, 0, 0 }, + {7, {0x91, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGE, 4, 0x60504030201}, 0, 0 }, + {9, {0xd1, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP_PGE, 6, 0x807060504030201}, 0, 0 }, + /* Packet Generation Disable */ + {1, {0x01}, 0, {INTEL_PT_TIP_PGD, 0, 0}, 0, 0 }, + {3, {0x21, 1, 2}, 0, {INTEL_PT_TIP_PGD, 1, 0x201}, 0, 0 }, + {5, {0x41, 1, 2, 3, 4}, 0, {INTEL_PT_TIP_PGD, 2, 0x4030201}, 0, 0 }, + {7, {0x61, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGD, 3, 0x60504030201}, 0, 0 }, + {7, {0x81, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_TIP_PGD, 4, 0x60504030201}, 0, 0 }, + {9, {0xc1, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_TIP_PGD, 6, 0x807060504030201}, 0, 0 }, + /* Flow Update Packet */ + {1, {0x1d}, 0, {INTEL_PT_FUP, 0, 0}, 0, 0 }, + {3, {0x3d, 1, 2}, 0, {INTEL_PT_FUP, 1, 0x201}, 0, 0 }, + {5, {0x5d, 1, 2, 3, 4}, 0, {INTEL_PT_FUP, 2, 0x4030201}, 0, 0 }, + {7, {0x7d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_FUP, 3, 0x60504030201}, 0, 0 }, + {7, {0x9d, 1, 2, 3, 4, 5, 6}, 0, {INTEL_PT_FUP, 4, 0x60504030201}, 0, 0 }, + {9, {0xdd, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_FUP, 6, 0x807060504030201}, 0, 0 }, + /* Paging Information Packet */ + {8, {0x02, 0x43, 2, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0x60504030201}, 0, 0 }, + {8, {0x02, 0x43, 3, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0x60504030201 | (1ULL << 63)}, 0, 0 }, + /* Mode Exec Packet */ + {2, {0x99, 0x00}, 0, {INTEL_PT_MODE_EXEC, 0, 16}, 0, 0 }, + {2, {0x99, 0x01}, 0, {INTEL_PT_MODE_EXEC, 0, 64}, 0, 0 }, + {2, {0x99, 0x02}, 0, {INTEL_PT_MODE_EXEC, 0, 32}, 0, 0 }, + /* Mode TSX Packet */ + {2, {0x99, 0x20}, 0, {INTEL_PT_MODE_TSX, 0, 0}, 0, 0 }, + {2, {0x99, 0x21}, 0, {INTEL_PT_MODE_TSX, 0, 1}, 0, 0 }, + {2, {0x99, 0x22}, 0, {INTEL_PT_MODE_TSX, 0, 2}, 0, 0 }, + /* Trace Stop Packet */ + {2, {0x02, 0x83}, 0, {INTEL_PT_TRACESTOP, 0, 0}, 0, 0 }, + /* Core:Bus Ratio Packet */ + {4, {0x02, 0x03, 0x12, 0}, 0, {INTEL_PT_CBR, 0, 0x12}, 0, 1 }, + /* Timestamp Counter Packet */ + {8, {0x19, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_TSC, 0, 0x7060504030201}, 0, 1 }, + /* Mini Time Counter Packet */ + {2, {0x59, 0x12}, 0, {INTEL_PT_MTC, 0, 0x12}, 0, 1 }, + /* TSC / MTC Alignment Packet */ + {7, {0x02, 0x73}, 0, {INTEL_PT_TMA, 0, 0}, 0, 1 }, + {7, {0x02, 0x73, 1, 2}, 0, {INTEL_PT_TMA, 0, 0x201}, 0, 1 }, + {7, {0x02, 0x73, 0, 0, 0, 0xff, 1}, 0, {INTEL_PT_TMA, 0x1ff, 0}, 0, 1 }, + {7, {0x02, 0x73, 0x80, 0xc0, 0, 0xff, 1}, 0, {INTEL_PT_TMA, 0x1ff, 0xc080}, 0, 1 }, + /* Cycle Count Packet */ + {1, {0x03}, 0, {INTEL_PT_CYC, 0, 0}, 0, 1 }, + {1, {0x0b}, 0, {INTEL_PT_CYC, 0, 1}, 0, 1 }, + {1, {0xfb}, 0, {INTEL_PT_CYC, 0, 0x1f}, 0, 1 }, + {2, {0x07, 2}, 0, {INTEL_PT_CYC, 0, 0x20}, 0, 1 }, + {2, {0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0xfff}, 0, 1 }, + {3, {0x07, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x1000}, 0, 1 }, + {3, {0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x7ffff}, 0, 1 }, + {4, {0x07, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x80000}, 0, 1 }, + {4, {0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x3ffffff}, 0, 1 }, + {5, {0x07, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x4000000}, 0, 1 }, + {5, {0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x1ffffffff}, 0, 1 }, + {6, {0x07, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x200000000}, 0, 1 }, + {6, {0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0xffffffffff}, 0, 1 }, + {7, {0x07, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x10000000000}, 0, 1 }, + {7, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x7fffffffffff}, 0, 1 }, + {8, {0x07, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x800000000000}, 0, 1 }, + {8, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x3fffffffffffff}, 0, 1 }, + {9, {0x07, 1, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x40000000000000}, 0, 1 }, + {9, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe}, 0, {INTEL_PT_CYC, 0, 0x1fffffffffffffff}, 0, 1 }, + {10, {0x07, 1, 1, 1, 1, 1, 1, 1, 1, 2}, 0, {INTEL_PT_CYC, 0, 0x2000000000000000}, 0, 1 }, + {10, {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xe}, 0, {INTEL_PT_CYC, 0, 0xffffffffffffffff}, 0, 1 }, + /* Virtual-Machine Control Structure Packet */ + {7, {0x02, 0xc8, 1, 2, 3, 4, 5}, 0, {INTEL_PT_VMCS, 5, 0x504030201}, 0, 0 }, + /* Overflow Packet */ + {2, {0x02, 0xf3}, 0, {INTEL_PT_OVF, 0, 0}, 0, 0 }, + {2, {0x02, 0xf3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_OVF, 0, 0}, 0, 0 }, + {2, {0x02, 0xf3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_OVF, 0, 0}, 0, 0 }, + /* Packet Stream Boundary*/ + {16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, 0, {INTEL_PT_PSB, 0, 0}, 0, 0 }, + {16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, INTEL_PT_BLK_4_CTX, {INTEL_PT_PSB, 0, 0}, 0, 0 }, + {16, {0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82, 0x02, 0x82}, INTEL_PT_BLK_8_CTX, {INTEL_PT_PSB, 0, 0}, 0, 0 }, + /* PSB End Packet */ + {2, {0x02, 0x23}, 0, {INTEL_PT_PSBEND, 0, 0}, 0, 0 }, + /* Maintenance Packet */ + {11, {0x02, 0xc3, 0x88, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_MNT, 0, 0x7060504030201}, 0, 1 }, + /* Write Data to PT Packet */ + {6, {0x02, 0x12, 1, 2, 3, 4}, 0, {INTEL_PT_PTWRITE, 0, 0x4030201}, 0, 0 }, + {10, {0x02, 0x32, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_PTWRITE, 1, 0x807060504030201}, 0, 0 }, + {6, {0x02, 0x92, 1, 2, 3, 4}, 0, {INTEL_PT_PTWRITE_IP, 0, 0x4030201}, 0, 0 }, + {10, {0x02, 0xb2, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_PTWRITE_IP, 1, 0x807060504030201}, 0, 0 }, + /* Execution Stop Packet */ + {2, {0x02, 0x62}, 0, {INTEL_PT_EXSTOP, 0, 0}, 0, 1 }, + {2, {0x02, 0xe2}, 0, {INTEL_PT_EXSTOP_IP, 0, 0}, 0, 1 }, + /* Monitor Wait Packet */ + {10, {0x02, 0xc2}, 0, {INTEL_PT_MWAIT, 0, 0}, 0, 0 }, + {10, {0x02, 0xc2, 1, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_MWAIT, 0, 0x807060504030201}, 0, 0 }, + {10, {0x02, 0xc2, 0xff, 2, 3, 4, 7, 6, 7, 8}, 0, {INTEL_PT_MWAIT, 0, 0x8070607040302ff}, 0, 0 }, + /* Power Entry Packet */ + {4, {0x02, 0x22}, 0, {INTEL_PT_PWRE, 0, 0}, 0, 1 }, + {4, {0x02, 0x22, 1, 2}, 0, {INTEL_PT_PWRE, 0, 0x0201}, 0, 1 }, + {4, {0x02, 0x22, 0x80, 0x34}, 0, {INTEL_PT_PWRE, 0, 0x3480}, 0, 1 }, + {4, {0x02, 0x22, 0x00, 0x56}, 0, {INTEL_PT_PWRE, 0, 0x5600}, 0, 1 }, + /* Power Exit Packet */ + {7, {0x02, 0xa2}, 0, {INTEL_PT_PWRX, 0, 0}, 0, 1 }, + {7, {0x02, 0xa2, 1, 2, 3, 4, 5}, 0, {INTEL_PT_PWRX, 0, 0x504030201}, 0, 1 }, + {7, {0x02, 0xa2, 0xff, 0xff, 0xff, 0xff, 0xff}, 0, {INTEL_PT_PWRX, 0, 0xffffffffff}, 0, 1 }, + /* Block Begin Packet */ + {3, {0x02, 0x63, 0x00}, 0, {INTEL_PT_BBP, 0, 0}, INTEL_PT_BLK_8_CTX, 0 }, + {3, {0x02, 0x63, 0x80}, 0, {INTEL_PT_BBP, 1, 0}, INTEL_PT_BLK_4_CTX, 0 }, + {3, {0x02, 0x63, 0x1f}, 0, {INTEL_PT_BBP, 0, 0x1f}, INTEL_PT_BLK_8_CTX, 0 }, + {3, {0x02, 0x63, 0x9f}, 0, {INTEL_PT_BBP, 1, 0x1f}, INTEL_PT_BLK_4_CTX, 0 }, + /* 4-byte Block Item Packet */ + {5, {0x04}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0, 0}, INTEL_PT_BLK_4_CTX, 0 }, + {5, {0xfc}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0x1f, 0}, INTEL_PT_BLK_4_CTX, 0 }, + {5, {0x04, 1, 2, 3, 4}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0, 0x04030201}, INTEL_PT_BLK_4_CTX, 0 }, + {5, {0xfc, 1, 2, 3, 4}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BIP, 0x1f, 0x04030201}, INTEL_PT_BLK_4_CTX, 0 }, + /* 8-byte Block Item Packet */ + {9, {0x04}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0, 0}, INTEL_PT_BLK_8_CTX, 0 }, + {9, {0xfc}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0x1f, 0}, INTEL_PT_BLK_8_CTX, 0 }, + {9, {0x04, 1, 2, 3, 4, 5, 6, 7, 8}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0, 0x0807060504030201}, INTEL_PT_BLK_8_CTX, 0 }, + {9, {0xfc, 1, 2, 3, 4, 5, 6, 7, 8}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BIP, 0x1f, 0x0807060504030201}, INTEL_PT_BLK_8_CTX, 0 }, + /* Block End Packet */ + {2, {0x02, 0x33}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 }, + {2, {0x02, 0xb3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 }, + {2, {0x02, 0x33}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 }, + {2, {0x02, 0xb3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 }, + /* Terminator */ + {0, {0}, 0, {0, 0, 0}, 0, 0 }, +}; + +static int dump_packet(struct intel_pt_pkt *packet, u8 *bytes, int len) +{ + char desc[INTEL_PT_PKT_DESC_MAX]; + int ret, i; + + for (i = 0; i < len; i++) + pr_debug(" %02x", bytes[i]); + for (; i < INTEL_PT_PKT_MAX_SZ; i++) + pr_debug(" "); + pr_debug(" "); + ret = intel_pt_pkt_desc(packet, desc, INTEL_PT_PKT_DESC_MAX); + if (ret < 0) { + pr_debug("intel_pt_pkt_desc failed!\n"); + return TEST_FAIL; + } + pr_debug("%s\n", desc); + + return TEST_OK; +} + +static void decoding_failed(struct test_data *d) +{ + pr_debug("Decoding failed!\n"); + pr_debug("Decoding: "); + dump_packet(&d->packet, d->bytes, d->len); +} + +static int fail(struct test_data *d, struct intel_pt_pkt *packet, int len, + enum intel_pt_pkt_ctx new_ctx) +{ + decoding_failed(d); + + if (len != d->len) + pr_debug("Expected length: %d Decoded length %d\n", + d->len, len); + + if (packet->type != d->packet.type) + pr_debug("Expected type: %d Decoded type %d\n", + d->packet.type, packet->type); + + if (packet->count != d->packet.count) + pr_debug("Expected count: %d Decoded count %d\n", + d->packet.count, packet->count); + + if (packet->payload != d->packet.payload) + pr_debug("Expected payload: 0x%llx Decoded payload 0x%llx\n", + (unsigned long long)d->packet.payload, + (unsigned long long)packet->payload); + + if (new_ctx != d->new_ctx) + pr_debug("Expected packet context: %d Decoded packet context %d\n", + d->new_ctx, new_ctx); + + return TEST_FAIL; +} + +static int test_ctx_unchanged(struct test_data *d, struct intel_pt_pkt *packet, + enum intel_pt_pkt_ctx ctx) +{ + enum intel_pt_pkt_ctx old_ctx = ctx; + + intel_pt_upd_pkt_ctx(packet, &ctx); + + if (ctx != old_ctx) { + decoding_failed(d); + pr_debug("Packet context changed!\n"); + return TEST_FAIL; + } + + return TEST_OK; +} + +static int test_one(struct test_data *d) +{ + struct intel_pt_pkt packet; + enum intel_pt_pkt_ctx ctx = d->ctx; + int ret; + + memset(&packet, 0xff, sizeof(packet)); + + /* Decode a packet */ + ret = intel_pt_get_packet(d->bytes, d->len, &packet, &ctx); + if (ret < 0 || ret > INTEL_PT_PKT_MAX_SZ) { + decoding_failed(d); + pr_debug("intel_pt_get_packet returned %d\n", ret); + return TEST_FAIL; + } + + /* Some packets must always leave the packet context unchanged */ + if (d->ctx_unchanged) { + int err; + + err = test_ctx_unchanged(d, &packet, INTEL_PT_NO_CTX); + if (err) + return err; + err = test_ctx_unchanged(d, &packet, INTEL_PT_BLK_4_CTX); + if (err) + return err; + err = test_ctx_unchanged(d, &packet, INTEL_PT_BLK_8_CTX); + if (err) + return err; + } + + /* Compare to the expected values */ + if (ret != d->len || packet.type != d->packet.type || + packet.count != d->packet.count || + packet.payload != d->packet.payload || ctx != d->new_ctx) + return fail(d, &packet, ret, ctx); + + pr_debug("Decoded ok:"); + ret = dump_packet(&d->packet, d->bytes, d->len); + + return ret; +} + +/* + * This test feeds byte sequences to the Intel PT packet decoder and checks the + * results. Changes to the packet context are also checked. + */ +int test__intel_pt_pkt_decoder(struct test *test __maybe_unused, int subtest __maybe_unused) +{ + struct test_data *d = data; + int ret; + + for (d = data; d->len; d++) { + ret = test_one(d); + if (ret) + return ret; + } + + return TEST_OK; +} diff --git a/tools/perf/arch/x86/tests/perf-time-to-tsc.c b/tools/perf/arch/x86/tests/perf-time-to-tsc.c index 7a7721604b86..909ead08a6f6 100644 --- a/tools/perf/arch/x86/tests/perf-time-to-tsc.c +++ b/tools/perf/arch/x86/tests/perf-time-to-tsc.c @@ -1,17 +1,24 @@ // SPDX-License-Identifier: GPL-2.0 #include <errno.h> #include <inttypes.h> +#include <limits.h> +#include <stdbool.h> #include <stdio.h> #include <unistd.h> #include <linux/types.h> #include <sys/prctl.h> +#include <perf/cpumap.h> +#include <perf/evlist.h> +#include <perf/mmap.h> +#include "debug.h" #include "parse-events.h" #include "evlist.h" #include "evsel.h" #include "thread_map.h" -#include "cpumap.h" +#include "record.h" #include "tsc.h" +#include "util/mmap.h" #include "tests/tests.h" #include "arch-tests.h" @@ -49,10 +56,10 @@ int test__perf_time_to_tsc(struct test *test __maybe_unused, int subtest __maybe }, .sample_time = true, }; - struct thread_map *threads = NULL; - struct cpu_map *cpus = NULL; - struct perf_evlist *evlist = NULL; - struct perf_evsel *evsel = NULL; + struct perf_thread_map *threads = NULL; + struct perf_cpu_map *cpus = NULL; + struct evlist *evlist = NULL; + struct evsel *evsel = NULL; int err = -1, ret, i; const char *comm1, *comm2; struct perf_tsc_conversion tc; @@ -60,34 +67,34 @@ int test__perf_time_to_tsc(struct test *test __maybe_unused, int subtest __maybe union perf_event *event; u64 test_tsc, comm1_tsc, comm2_tsc; u64 test_time, comm1_time = 0, comm2_time = 0; - struct perf_mmap *md; + struct mmap *md; threads = thread_map__new(-1, getpid(), UINT_MAX); CHECK_NOT_NULL__(threads); - cpus = cpu_map__new(NULL); + cpus = perf_cpu_map__new(NULL); CHECK_NOT_NULL__(cpus); - evlist = perf_evlist__new(); + evlist = evlist__new(); CHECK_NOT_NULL__(evlist); - perf_evlist__set_maps(evlist, cpus, threads); + perf_evlist__set_maps(&evlist->core, cpus, threads); CHECK__(parse_events(evlist, "cycles:u", NULL)); perf_evlist__config(evlist, &opts, NULL); - evsel = perf_evlist__first(evlist); + evsel = evlist__first(evlist); - evsel->attr.comm = 1; - evsel->attr.disabled = 1; - evsel->attr.enable_on_exec = 0; + evsel->core.attr.comm = 1; + evsel->core.attr.disabled = 1; + evsel->core.attr.enable_on_exec = 0; - CHECK__(perf_evlist__open(evlist)); + CHECK__(evlist__open(evlist)); - CHECK__(perf_evlist__mmap(evlist, UINT_MAX)); + CHECK__(evlist__mmap(evlist, UINT_MAX)); - pc = evlist->mmap[0].base; + pc = evlist->mmap[0].core.base; ret = perf_read_tsc_conversion(pc, &tc); if (ret) { if (ret == -EOPNOTSUPP) { @@ -97,7 +104,7 @@ int test__perf_time_to_tsc(struct test *test __maybe_unused, int subtest __maybe goto out_err; } - perf_evlist__enable(evlist); + evlist__enable(evlist); comm1 = "Test COMM 1"; CHECK__(prctl(PR_SET_NAME, (unsigned long)comm1, 0, 0, 0)); @@ -107,14 +114,14 @@ int test__perf_time_to_tsc(struct test *test __maybe_unused, int subtest __maybe comm2 = "Test COMM 2"; CHECK__(prctl(PR_SET_NAME, (unsigned long)comm2, 0, 0, 0)); - perf_evlist__disable(evlist); + evlist__disable(evlist); - for (i = 0; i < evlist->nr_mmaps; i++) { + for (i = 0; i < evlist->core.nr_mmaps; i++) { md = &evlist->mmap[i]; - if (perf_mmap__read_init(md) < 0) + if (perf_mmap__read_init(&md->core) < 0) continue; - while ((event = perf_mmap__read_event(md)) != NULL) { + while ((event = perf_mmap__read_event(&md->core)) != NULL) { struct perf_sample sample; if (event->header.type != PERF_RECORD_COMM || @@ -133,9 +140,9 @@ int test__perf_time_to_tsc(struct test *test __maybe_unused, int subtest __maybe comm2_time = sample.time; } next_event: - perf_mmap__consume(md); + perf_mmap__consume(&md->core); } - perf_mmap__read_done(md); + perf_mmap__read_done(&md->core); } if (!comm1_time || !comm2_time) @@ -163,6 +170,6 @@ next_event: err = 0; out_err: - perf_evlist__delete(evlist); + evlist__delete(evlist); return err; } diff --git a/tools/perf/arch/x86/tests/rdpmc.c b/tools/perf/arch/x86/tests/rdpmc.c index 7a11f02d6c6c..1ea916656a2d 100644 --- a/tools/perf/arch/x86/tests/rdpmc.c +++ b/tools/perf/arch/x86/tests/rdpmc.c @@ -6,12 +6,14 @@ #include <sys/mman.h> #include <sys/types.h> #include <sys/wait.h> +#include <linux/string.h> #include <linux/types.h> -#include "perf.h" +#include "perf-sys.h" #include "debug.h" #include "tests/tests.h" #include "cloexec.h" -#include "util.h" +#include "event.h" +#include <internal/lib.h> // page_size #include "arch-tests.h" static u64 rdpmc(unsigned int counter) |
