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-rw-r--r--include/asm-avr32/arch-at32ap/gpio.h2
-rw-r--r--include/asm-avr32/cache.h9
-rw-r--r--include/asm-blackfin/blackfin.h6
-rw-r--r--include/asm-blackfin/gpio.h1
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h22
-rw-r--r--include/asm-blackfin/macros.h95
-rw-r--r--include/asm-mips/mips-boards/generic.h22
-rw-r--r--include/asm-mips/mips-boards/msc01_pci.h1
8 files changed, 59 insertions, 99 deletions
diff --git a/include/asm-avr32/arch-at32ap/gpio.h b/include/asm-avr32/arch-at32ap/gpio.h
index 80a21aa9ae77..af7f9535bab3 100644
--- a/include/asm-avr32/arch-at32ap/gpio.h
+++ b/include/asm-avr32/arch-at32ap/gpio.h
@@ -14,6 +14,8 @@ int gpio_direction_output(unsigned int gpio, int value);
int gpio_get_value(unsigned int gpio);
void gpio_set_value(unsigned int gpio, int value);
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+
static inline int gpio_to_irq(unsigned int gpio)
{
return gpio + GPIO_IRQ_BASE;
diff --git a/include/asm-avr32/cache.h b/include/asm-avr32/cache.h
index dabb955f3c00..d3cf35ab11ab 100644
--- a/include/asm-avr32/cache.h
+++ b/include/asm-avr32/cache.h
@@ -4,6 +4,15 @@
#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+/*
+ * Memory returned by kmalloc() may be used for DMA, so we must make
+ * sure that all such allocations are cache aligned. Otherwise,
+ * unrelated code may cause parts of the buffer to be read into the
+ * cache before the transfer is done, causing old data to be seen by
+ * the CPU.
+ */
+#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
+
#ifndef __ASSEMBLER__
struct cache_info {
unsigned int ways;
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index 14e58de73973..db3b615ffbab 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -6,7 +6,11 @@
#ifndef _BLACKFIN_H_
#define _BLACKFIN_H_
-#include <asm/macros.h>
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
#include <asm/mach/blackfin.h>
#include <asm/bfin-global.h>
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index aa0d5503e232..d98d77ad71f7 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -332,6 +332,7 @@ struct gpio_port_s {
unsigned short inen;
unsigned short fer;
+ unsigned short reserved;
};
#endif /*CONFIG_PM*/
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index 76103526aec1..be1ece8c0c27 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -42,6 +42,12 @@
#if defined(ANOMALY_05000198)
+#define bfin_read8(addr) ({ unsigned char __v; \
+ __asm__ __volatile__ ("NOP;\n\t" \
+ "%0 = b[%1] (z);\n\t" \
+ : "=d"(__v) : "a"(addr)); \
+ __v; })
+
#define bfin_read16(addr) ({ unsigned __v; \
__asm__ __volatile__ ("NOP;\n\t"\
"%0 = w[%1] (z);\n\t"\
@@ -52,6 +58,11 @@
"%0 = [%1];\n\t"\
: "=d"(__v) : "a"(addr)); __v; })
+#define bfin_write8(addr, val) ({ \
+ __asm__ __volatile__ ("NOP;\n\t" \
+ "b[%0] = %1;\n\t" \
+ : : "a"(addr), "d"(val) : "memory");})
+
#define bfin_write16(addr,val) ({\
__asm__ __volatile__ ("NOP;\n\t"\
"w[%0] = %1;\n\t"\
@@ -64,6 +75,12 @@
#else
+#define bfin_read8(addr) ({ unsigned char __v; \
+ __asm__ __volatile__ ( \
+ "%0 = b[%1] (z);\n\t" \
+ :"=d"(__v) : "a"(addr)); \
+ __v; })
+
#define bfin_read16(addr) ({ unsigned __v; \
__asm__ __volatile__ (\
"%0 = w[%1] (z);\n\t"\
@@ -74,6 +91,11 @@
"%0 = [%1];\n\t"\
: "=d"(__v) : "a"(addr)); __v; })
+#define bfin_write8(addr, val) ({ \
+ __asm__ __volatile__ ( \
+ "b[%0] = %1; \n\t" \
+ ::"a"(addr), "d"(val) : "memory");})
+
#define bfin_write16(addr,val) ({\
__asm__ __volatile__ (\
"w[%0] = %1;\n\t"\
diff --git a/include/asm-blackfin/macros.h b/include/asm-blackfin/macros.h
index c0c04a2f2dd5..e69de29bb2d1 100644
--- a/include/asm-blackfin/macros.h
+++ b/include/asm-blackfin/macros.h
@@ -1,95 +0,0 @@
-/************************************************************************
- *
- * macros.h
- *
- * (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved.
- *
- ************************************************************************/
-
-/* Defines various assembly macros. */
-
-#ifndef _MACROS_H
-#define _MACROS_H
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-/*
- * Set the corresponding bits in a System Register (SR);
- * All bits set in "mask" will be set in the system register
- * specified by "sys_reg" bitset_SR(sys_reg, mask), where
- * sys_reg is the system register and mask are the bits to be set.
- */
-#define bitset_SR(sys_reg, mask)\
- [--SP] = (R7:6);\
- r7 = sys_reg;\
- r6.l = (mask) & 0xffff;\
- r6.h = (mask) >> 16;\
- r7 = r7 | r6;\
- sys_reg = r7;\
- csync;\
- (R7:6) = [SP++]
-
-/*
- * Clear the corresponding bits in a System Register (SR);
- * All bits set in "mask" will be cleared in the SR
- * specified by "sys_reg" bitclr_SR(sys_reg, mask), where
- * sys_reg is the SR and mask are the bits to be cleared.
- */
-#define bitclr_SR(sys_reg, mask)\
- [--SP] = (R7:6);\
- r7 = sys_reg;\
- r7 =~ r7;\
- r6.l = (mask) & 0xffff;\
- r6.h = (mask) >> 16;\
- r7 = r7 | r6;\
- r7 =~ r7;\
- sys_reg = r7;\
- csync;\
- (R7:6) = [SP++]
-
-/*
- * Set the corresponding bits in a Memory Mapped Register (MMR);
- * All bits set in "mask" will be set in the MMR specified by "mmr_reg"
- * bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are
- * the bits to be set.
- */
-#define bitset_MMR(mmr_reg, mask)\
- [--SP] = (R7:6);\
- [--SP] = P5;\
- p5.l = mmr_reg & 0xffff;\
- p5.h = mmr_reg >> 16;\
- r7 = [p5];\
- r6.l = (mask) & 0xffff;\
- r6.h = (mask) >> 16;\
- r7 = r7 | r6;\
- [p5] = r7;\
- csync;\
- p5 = [SP++];\
- (R7:6) = [SP++]
-
-/*
- * Clear the corresponding bits in a Memory Mapped Register (MMR);
- * All bits set in "mask" will be cleared in the MMR specified by "mmr_reg"
- * bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are
- * the bits to be cleared.
- */
-#define bitclr_MMR(mmr_reg, mask)\
- [--SP] = (R7:6);\
- [--SP] = P5;\
- p5.l = mmr_reg & 0xffff;\
- p5.h = mmr_reg >> 16;\
- r7 = [p5];\
- r7 =~ r7;\
- r6.l = (mask) & 0xffff;\
- r6.h = (mask) >> 16;\
- r7 = r7 | r6;\
- r7 =~ r7;\
- [p5] = r7;\
- csync;\
- p5 = [SP++];\
- (R7:6) = [SP++]
-
-#endif /* _MACROS_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index b98f1658cfd0..c8ebcc3e1267 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -73,12 +73,28 @@
* CoreEMUL with Bonito System Controller is treated like a Core20K
* CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
*/
-#define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63
-#define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65
+#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
+#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
-extern unsigned int mips_revision_corid;
+extern int mips_revision_corid;
+
+#define MIPS_REVISION_SCON_OTHER 0
+#define MIPS_REVISION_SCON_SOCITSC 1
+#define MIPS_REVISION_SCON_SOCITSCP 2
+
+/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
+#define MIPS_REVISION_SCON_UNKNOWN -1
+#define MIPS_REVISION_SCON_GT64120 -2
+#define MIPS_REVISION_SCON_BONITO -3
+#define MIPS_REVISION_SCON_BRTL -4
+#define MIPS_REVISION_SCON_SOCIT -5
+#define MIPS_REVISION_SCON_ROCIT -6
+
+#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
+
+extern int mips_revision_sconid;
#ifdef CONFIG_PCI
extern void mips_pcibios_init(void);
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 8eaefb837b9d..e036b7dd6deb 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -208,6 +208,7 @@
* latter, they should be moved elsewhere.
*/
#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
+#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000
extern unsigned long _pcictrl_msc;
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