diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/r8a774b1-cpg-mssr.h | 57 | ||||
| -rw-r--r-- | include/dt-bindings/power/r8a774b1-sysc.h | 26 | ||||
| -rw-r--r-- | include/dt-bindings/reset/amlogic,meson-a1-reset.h | 74 | ||||
| -rw-r--r-- | include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h | 2 |
4 files changed, 159 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h new file mode 100644 index 000000000000..1355451b74b0 --- /dev/null +++ b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a774b1 CPG Core Clocks */ +#define R8A774B1_CLK_Z 0 +#define R8A774B1_CLK_ZG 1 +#define R8A774B1_CLK_ZTR 2 +#define R8A774B1_CLK_ZTRD2 3 +#define R8A774B1_CLK_ZT 4 +#define R8A774B1_CLK_ZX 5 +#define R8A774B1_CLK_S0D1 6 +#define R8A774B1_CLK_S0D2 7 +#define R8A774B1_CLK_S0D3 8 +#define R8A774B1_CLK_S0D4 9 +#define R8A774B1_CLK_S0D6 10 +#define R8A774B1_CLK_S0D8 11 +#define R8A774B1_CLK_S0D12 12 +#define R8A774B1_CLK_S1D2 13 +#define R8A774B1_CLK_S1D4 14 +#define R8A774B1_CLK_S2D1 15 +#define R8A774B1_CLK_S2D2 16 +#define R8A774B1_CLK_S2D4 17 +#define R8A774B1_CLK_S3D1 18 +#define R8A774B1_CLK_S3D2 19 +#define R8A774B1_CLK_S3D4 20 +#define R8A774B1_CLK_LB 21 +#define R8A774B1_CLK_CL 22 +#define R8A774B1_CLK_ZB3 23 +#define R8A774B1_CLK_ZB3D2 24 +#define R8A774B1_CLK_CR 25 +#define R8A774B1_CLK_DDR 26 +#define R8A774B1_CLK_SD0H 27 +#define R8A774B1_CLK_SD0 28 +#define R8A774B1_CLK_SD1H 29 +#define R8A774B1_CLK_SD1 30 +#define R8A774B1_CLK_SD2H 31 +#define R8A774B1_CLK_SD2 32 +#define R8A774B1_CLK_SD3H 33 +#define R8A774B1_CLK_SD3 34 +#define R8A774B1_CLK_RPC 35 +#define R8A774B1_CLK_RPCD2 36 +#define R8A774B1_CLK_MSO 37 +#define R8A774B1_CLK_HDMI 38 +#define R8A774B1_CLK_CSI0 39 +#define R8A774B1_CLK_CP 40 +#define R8A774B1_CLK_CPEX 41 +#define R8A774B1_CLK_R 42 +#define R8A774B1_CLK_OSC 43 +#define R8A774B1_CLK_CANFD 44 + +#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h new file mode 100644 index 000000000000..373736402f04 --- /dev/null +++ b/include/dt-bindings/power/r8a774b1-sysc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774B1_PD_CA57_CPU0 0 +#define R8A774B1_PD_CA57_CPU1 1 +#define R8A774B1_PD_A3VP 9 +#define R8A774B1_PD_CA57_SCU 12 +#define R8A774B1_PD_A3VC 14 +#define R8A774B1_PD_3DG_A 17 +#define R8A774B1_PD_3DG_B 18 +#define R8A774B1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774B1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */ diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h new file mode 100644 index 000000000000..f1a3a797540d --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + * + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H + +/* RESET0 */ +/* 0 */ +#define RESET_AM2AXI_VAD 1 +/* 2-3 */ +#define RESET_PSRAM 4 +#define RESET_PAD_CTRL 5 +/* 6 */ +#define RESET_TEMP_SENSOR 7 +#define RESET_AM2AXI_DEV 8 +/* 9 */ +#define RESET_SPICC_A 10 +#define RESET_MSR_CLK 11 +#define RESET_AUDIO 12 +#define RESET_ANALOG_CTRL 13 +#define RESET_SAR_ADC 14 +#define RESET_AUDIO_VAD 15 +#define RESET_CEC 16 +#define RESET_PWM_EF 17 +#define RESET_PWM_CD 18 +#define RESET_PWM_AB 19 +/* 20 */ +#define RESET_IR_CTRL 21 +#define RESET_I2C_S_A 22 +/* 23 */ +#define RESET_I2C_M_D 24 +#define RESET_I2C_M_C 25 +#define RESET_I2C_M_B 26 +#define RESET_I2C_M_A 27 +#define RESET_I2C_PROD_AHB 28 +#define RESET_I2C_PROD 29 +/* 30-31 */ + +/* RESET1 */ +#define RESET_ACODEC 32 +#define RESET_DMA 33 +#define RESET_SD_EMMC_A 34 +/* 35 */ +#define RESET_USBCTRL 36 +/* 37 */ +#define RESET_USBPHY 38 +/* 39-41 */ +#define RESET_RSA 42 +#define RESET_DMC 43 +/* 44 */ +#define RESET_IRQ_CTRL 45 +/* 46 */ +#define RESET_NIC_VAD 47 +#define RESET_NIC_AXI 48 +#define RESET_RAMA 49 +#define RESET_RAMB 50 +/* 51-52 */ +#define RESET_ROM 53 +#define RESET_SPIFC 54 +#define RESET_GIC 55 +#define RESET_UART_C 56 +#define RESET_UART_B 57 +#define RESET_UART_A 58 +#define RESET_OSC_RING 59 +/* 60-63 */ + +/* RESET2 */ +/* 64-95 */ + +#endif diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h index 05c36367875c..1ef807856cb8 100644 --- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +++ b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h @@ -13,5 +13,7 @@ #define AXG_ARB_FRDDR_A 3 #define AXG_ARB_FRDDR_B 4 #define AXG_ARB_FRDDR_C 5 +#define AXG_ARB_TODDR_D 6 +#define AXG_ARB_FRDDR_D 7 #endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ |
