diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/exynos4415.h | 360 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos7-clk.h | 92 | ||||
| -rw-r--r-- | include/dt-bindings/clock/marvell,mmp2.h | 74 | ||||
| -rw-r--r-- | include/dt-bindings/clock/marvell,pxa168.h | 57 | ||||
| -rw-r--r-- | include/dt-bindings/clock/marvell,pxa910.h | 54 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3288-cru.h | 13 | ||||
| -rw-r--r-- | include/dt-bindings/dma/at91.h | 25 | ||||
| -rw-r--r-- | include/dt-bindings/interrupt-controller/arm-gic.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/interrupt-controller/mips-gic.h | 9 | ||||
| -rw-r--r-- | include/dt-bindings/phy/phy.h | 19 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 142 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 44 | ||||
| -rw-r--r-- | include/dt-bindings/thermal/tegra124-soctherm.h | 13 | ||||
| -rw-r--r-- | include/dt-bindings/thermal/thermal.h | 2 |
14 files changed, 905 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/exynos4415.h b/include/dt-bindings/clock/exynos4415.h new file mode 100644 index 000000000000..7eed55100721 --- /dev/null +++ b/include/dt-bindings/clock/exynos4415.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Chanwoo Choi <cw00.choi@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Samsung Exynos4415 clock controllers. + */ + +#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H +#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H + +/* + * Let each exported clock get a unique index, which is used on DT-enabled + * platforms to lookup the clock from a clock specifier. These indices are + * therefore considered an ABI and so must not be changed. This implies + * that new clocks should be added either in free spaces between clock groups + * or at the end. + */ + +/* + * Main CMU + */ + +#define CLK_OSCSEL 1 +#define CLK_FIN_PLL 2 +#define CLK_FOUT_APLL 3 +#define CLK_FOUT_MPLL 4 +#define CLK_FOUT_EPLL 5 +#define CLK_FOUT_G3D_PLL 6 +#define CLK_FOUT_ISP_PLL 7 +#define CLK_FOUT_DISP_PLL 8 + +/* Muxes */ +#define CLK_MOUT_MPLL_USER_L 16 +#define CLK_MOUT_GDL 17 +#define CLK_MOUT_MPLL_USER_R 18 +#define CLK_MOUT_GDR 19 +#define CLK_MOUT_EBI 20 +#define CLK_MOUT_ACLK_200 21 +#define CLK_MOUT_ACLK_160 22 +#define CLK_MOUT_ACLK_100 23 +#define CLK_MOUT_ACLK_266 24 +#define CLK_MOUT_G3D_PLL 25 +#define CLK_MOUT_EPLL 26 +#define CLK_MOUT_EBI_1 27 +#define CLK_MOUT_ISP_PLL 28 +#define CLK_MOUT_DISP_PLL 29 +#define CLK_MOUT_MPLL_USER_T 30 +#define CLK_MOUT_ACLK_400_MCUISP 31 +#define CLK_MOUT_G3D_PLLSRC 32 +#define CLK_MOUT_CSIS1 33 +#define CLK_MOUT_CSIS0 34 +#define CLK_MOUT_CAM1 35 +#define CLK_MOUT_FIMC3_LCLK 36 +#define CLK_MOUT_FIMC2_LCLK 37 +#define CLK_MOUT_FIMC1_LCLK 38 +#define CLK_MOUT_FIMC0_LCLK 39 +#define CLK_MOUT_MFC 40 +#define CLK_MOUT_MFC_1 41 +#define CLK_MOUT_MFC_0 42 +#define CLK_MOUT_G3D 43 +#define CLK_MOUT_G3D_1 44 +#define CLK_MOUT_G3D_0 45 +#define CLK_MOUT_MIPI0 46 +#define CLK_MOUT_FIMD0 47 +#define CLK_MOUT_TSADC_ISP 48 +#define CLK_MOUT_UART_ISP 49 +#define CLK_MOUT_SPI1_ISP 50 +#define CLK_MOUT_SPI0_ISP 51 +#define CLK_MOUT_PWM_ISP 52 +#define CLK_MOUT_AUDIO0 53 +#define CLK_MOUT_TSADC 54 +#define CLK_MOUT_MMC2 55 +#define CLK_MOUT_MMC1 56 +#define CLK_MOUT_MMC0 57 +#define CLK_MOUT_UART3 58 +#define CLK_MOUT_UART2 59 +#define CLK_MOUT_UART1 60 +#define CLK_MOUT_UART0 61 +#define CLK_MOUT_SPI2 62 +#define CLK_MOUT_SPI1 63 +#define CLK_MOUT_SPI0 64 +#define CLK_MOUT_SPDIF 65 +#define CLK_MOUT_AUDIO2 66 +#define CLK_MOUT_AUDIO1 67 +#define CLK_MOUT_MPLL_USER_C 68 +#define CLK_MOUT_HPM 69 +#define CLK_MOUT_CORE 70 +#define CLK_MOUT_APLL 71 +#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72 +#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73 +#define CLK_MOUT_JPEG 74 +#define CLK_MOUT_JPEG1 75 +#define CLK_MOUT_JPEG0 76 +#define CLK_MOUT_ACLK_ISP0_300 77 +#define CLK_MOUT_ACLK_ISP0_400 78 +#define CLK_MOUT_ACLK_ISP0_300_USER 79 +#define CLK_MOUT_ACLK_ISP1_300 80 +#define CLK_MOUT_ACLK_ISP1_300_USER 81 +#define CLK_MOUT_HDMI 82 + +/* Dividers */ +#define CLK_DIV_GPL 90 +#define CLK_DIV_GDL 91 +#define CLK_DIV_GPR 92 +#define CLK_DIV_GDR 93 +#define CLK_DIV_ACLK_400_MCUISP 94 +#define CLK_DIV_EBI 95 +#define CLK_DIV_ACLK_200 96 +#define CLK_DIV_ACLK_160 97 +#define CLK_DIV_ACLK_100 98 +#define CLK_DIV_ACLK_266 99 +#define CLK_DIV_CSIS1 100 +#define CLK_DIV_CSIS0 101 +#define CLK_DIV_CAM1 102 +#define CLK_DIV_FIMC3_LCLK 103 +#define CLK_DIV_FIMC2_LCLK 104 +#define CLK_DIV_FIMC1_LCLK 105 +#define CLK_DIV_FIMC0_LCLK 106 +#define CLK_DIV_TV_BLK 107 +#define CLK_DIV_MFC 108 +#define CLK_DIV_G3D 109 +#define CLK_DIV_MIPI0_PRE 110 +#define CLK_DIV_MIPI0 111 +#define CLK_DIV_FIMD0 112 +#define CLK_DIV_UART_ISP 113 +#define CLK_DIV_SPI1_ISP_PRE 114 +#define CLK_DIV_SPI1_ISP 115 +#define CLK_DIV_SPI0_ISP_PRE 116 +#define CLK_DIV_SPI0_ISP 117 +#define CLK_DIV_PWM_ISP 118 +#define CLK_DIV_PCM0 119 +#define CLK_DIV_AUDIO0 120 +#define CLK_DIV_TSADC_PRE 121 +#define CLK_DIV_TSADC 122 +#define CLK_DIV_MMC1_PRE 123 +#define CLK_DIV_MMC1 124 +#define CLK_DIV_MMC0_PRE 125 +#define CLK_DIV_MMC0 126 +#define CLK_DIV_MMC2_PRE 127 +#define CLK_DIV_MMC2 128 +#define CLK_DIV_UART3 129 +#define CLK_DIV_UART2 130 +#define CLK_DIV_UART1 131 +#define CLK_DIV_UART0 132 +#define CLK_DIV_SPI1_PRE 133 +#define CLK_DIV_SPI1 134 +#define CLK_DIV_SPI0_PRE 135 +#define CLK_DIV_SPI0 136 +#define CLK_DIV_SPI2_PRE 137 +#define CLK_DIV_SPI2 138 +#define CLK_DIV_PCM2 139 +#define CLK_DIV_AUDIO2 140 +#define CLK_DIV_PCM1 141 +#define CLK_DIV_AUDIO1 142 +#define CLK_DIV_I2S1 143 +#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144 +#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145 +#define CLK_DIV_JPEG 146 +#define CLK_DIV_CORE2 147 +#define CLK_DIV_APLL 148 +#define CLK_DIV_PCLK_DBG 149 +#define CLK_DIV_ATB 150 +#define CLK_DIV_PERIPH 151 +#define CLK_DIV_COREM1 152 +#define CLK_DIV_COREM0 153 +#define CLK_DIV_CORE 154 +#define CLK_DIV_HPM 155 +#define CLK_DIV_COPY 156 + +/* Gates */ +#define CLK_ASYNC_G3D 180 +#define CLK_ASYNC_MFCL 181 +#define CLK_ASYNC_TVX 182 +#define CLK_PPMULEFT 183 +#define CLK_GPIO_LEFT 184 +#define CLK_PPMUIMAGE 185 +#define CLK_QEMDMA2 186 +#define CLK_QEROTATOR 187 +#define CLK_SMMUMDMA2 188 +#define CLK_SMMUROTATOR 189 +#define CLK_MDMA2 190 +#define CLK_ROTATOR 191 +#define CLK_ASYNC_ISPMX 192 +#define CLK_ASYNC_MAUDIOX 193 +#define CLK_ASYNC_MFCR 194 +#define CLK_ASYNC_FSYSD 195 +#define CLK_ASYNC_LCD0X 196 +#define CLK_ASYNC_CAMX 197 +#define CLK_PPMURIGHT 198 +#define CLK_GPIO_RIGHT 199 +#define CLK_ANTIRBK_APBIF 200 +#define CLK_EFUSE_WRITER_APBIF 201 +#define CLK_MONOCNT 202 +#define CLK_TZPC6 203 +#define CLK_PROVISIONKEY1 204 +#define CLK_PROVISIONKEY0 205 +#define CLK_CMU_ISPPART 206 +#define CLK_TMU_APBIF 207 +#define CLK_KEYIF 208 +#define CLK_RTC 209 +#define CLK_WDT 210 +#define CLK_MCT 211 +#define CLK_SECKEY 212 +#define CLK_HDMI_CEC 213 +#define CLK_TZPC5 214 +#define CLK_TZPC4 215 +#define CLK_TZPC3 216 +#define CLK_TZPC2 217 +#define CLK_TZPC1 218 +#define CLK_TZPC0 219 +#define CLK_CMU_COREPART 220 +#define CLK_CMU_TOPPART 221 +#define CLK_PMU_APBIF 222 +#define CLK_SYSREG 223 +#define CLK_CHIP_ID 224 +#define CLK_SMMUFIMC_LITE2 225 +#define CLK_FIMC_LITE2 226 +#define CLK_PIXELASYNCM1 227 +#define CLK_PIXELASYNCM0 228 +#define CLK_PPMUCAMIF 229 +#define CLK_SMMUJPEG 230 +#define CLK_SMMUFIMC3 231 +#define CLK_SMMUFIMC2 232 +#define CLK_SMMUFIMC1 233 +#define CLK_SMMUFIMC0 234 +#define CLK_JPEG 235 +#define CLK_CSIS1 236 +#define CLK_CSIS0 237 +#define CLK_FIMC3 238 +#define CLK_FIMC2 239 +#define CLK_FIMC1 240 +#define CLK_FIMC0 241 +#define CLK_PPMUTV 242 +#define CLK_SMMUTV 243 +#define CLK_HDMI 244 +#define CLK_MIXER 245 +#define CLK_VP 246 +#define CLK_PPMUMFC_R 247 +#define CLK_PPMUMFC_L 248 +#define CLK_SMMUMFC_R 249 +#define CLK_SMMUMFC_L 250 +#define CLK_MFC 251 +#define CLK_PPMUG3D 252 +#define CLK_G3D 253 +#define CLK_PPMULCD0 254 +#define CLK_SMMUFIMD0 255 +#define CLK_DSIM0 256 +#define CLK_SMIES 257 +#define CLK_MIE0 258 +#define CLK_FIMD0 259 +#define CLK_TSADC 260 +#define CLK_PPMUFILE 261 +#define CLK_NFCON 262 +#define CLK_USBDEVICE 263 +#define CLK_USBHOST 264 +#define CLK_SROMC 265 +#define CLK_SDMMC2 266 +#define CLK_SDMMC1 267 +#define CLK_SDMMC0 268 +#define CLK_PDMA1 269 +#define CLK_PDMA0 270 +#define CLK_SPDIF 271 +#define CLK_PWM 272 +#define CLK_PCM2 273 +#define CLK_PCM1 274 +#define CLK_I2S1 275 +#define CLK_SPI2 276 +#define CLK_SPI1 277 +#define CLK_SPI0 278 +#define CLK_I2CHDMI 279 +#define CLK_I2C7 280 +#define CLK_I2C6 281 +#define CLK_I2C5 282 +#define CLK_I2C4 283 +#define CLK_I2C3 284 +#define CLK_I2C2 285 +#define CLK_I2C1 286 +#define CLK_I2C0 287 +#define CLK_UART3 288 +#define CLK_UART2 289 +#define CLK_UART1 290 +#define CLK_UART0 291 + +/* Special clocks */ +#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330 +#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331 +#define CLK_SCLK_JPEG 332 +#define CLK_SCLK_CSIS1 333 +#define CLK_SCLK_CSIS0 334 +#define CLK_SCLK_CAM1 335 +#define CLK_SCLK_FIMC3_LCLK 336 +#define CLK_SCLK_FIMC2_LCLK 337 +#define CLK_SCLK_FIMC1_LCLK 338 +#define CLK_SCLK_FIMC0_LCLK 339 +#define CLK_SCLK_PIXEL 340 +#define CLK_SCLK_HDMI 341 +#define CLK_SCLK_MIXER 342 +#define CLK_SCLK_MFC 343 +#define CLK_SCLK_G3D 344 +#define CLK_SCLK_MIPIDPHY4L 345 +#define CLK_SCLK_MIPI0 346 +#define CLK_SCLK_MDNIE0 347 +#define CLK_SCLK_FIMD0 348 +#define CLK_SCLK_PCM0 349 +#define CLK_SCLK_AUDIO0 350 +#define CLK_SCLK_TSADC 351 +#define CLK_SCLK_EBI 352 +#define CLK_SCLK_MMC2 353 +#define CLK_SCLK_MMC1 354 +#define CLK_SCLK_MMC0 355 +#define CLK_SCLK_I2S 356 +#define CLK_SCLK_PCM2 357 +#define CLK_SCLK_PCM1 358 +#define CLK_SCLK_AUDIO2 359 +#define CLK_SCLK_AUDIO1 360 +#define CLK_SCLK_SPDIF 361 +#define CLK_SCLK_SPI2 362 +#define CLK_SCLK_SPI1 363 +#define CLK_SCLK_SPI0 364 +#define CLK_SCLK_UART3 365 +#define CLK_SCLK_UART2 366 +#define CLK_SCLK_UART1 367 +#define CLK_SCLK_UART0 368 +#define CLK_SCLK_HDMIPHY 369 + +/* + * Total number of clocks of main CMU. + * NOTE: Must be equal to last clock ID increased by one. + */ +#define CLK_NR_CLKS 370 + +/* + * CMU DMC + */ +#define CLK_DMC_FOUT_MPLL 1 +#define CLK_DMC_FOUT_BPLL 2 + +#define CLK_DMC_MOUT_MPLL 3 +#define CLK_DMC_MOUT_BPLL 4 +#define CLK_DMC_MOUT_DPHY 5 +#define CLK_DMC_MOUT_DMC_BUS 6 + +#define CLK_DMC_DIV_DMC 7 +#define CLK_DMC_DIV_DPHY 8 +#define CLK_DMC_DIV_DMC_PRE 9 +#define CLK_DMC_DIV_DMCP 10 +#define CLK_DMC_DIV_DMCD 11 +#define CLK_DMC_DIV_MPLL_PRE 12 + +/* + * Total number of clocks of CMU_DMC. + * NOTE: Must be equal to highest clock ID increased by one. + */ +#define NR_CLKS_DMC 13 + +#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */ diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h new file mode 100644 index 000000000000..8e4681b07ae7 --- /dev/null +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H +#define _DT_BINDINGS_CLOCK_EXYNOS7_H + +/* TOPC */ +#define DOUT_ACLK_PERIS 1 +#define DOUT_SCLK_BUS0_PLL 2 +#define DOUT_SCLK_BUS1_PLL 3 +#define DOUT_SCLK_CC_PLL 4 +#define DOUT_SCLK_MFC_PLL 5 +#define DOUT_ACLK_CCORE_133 6 +#define TOPC_NR_CLK 7 + +/* TOP0 */ +#define DOUT_ACLK_PERIC1 1 +#define DOUT_ACLK_PERIC0 2 +#define CLK_SCLK_UART0 3 +#define CLK_SCLK_UART1 4 +#define CLK_SCLK_UART2 5 +#define CLK_SCLK_UART3 6 +#define TOP0_NR_CLK 7 + +/* TOP1 */ +#define DOUT_ACLK_FSYS1_200 1 +#define DOUT_ACLK_FSYS0_200 2 +#define DOUT_SCLK_MMC2 3 +#define DOUT_SCLK_MMC1 4 +#define DOUT_SCLK_MMC0 5 +#define CLK_SCLK_MMC2 6 +#define CLK_SCLK_MMC1 7 +#define CLK_SCLK_MMC0 8 +#define TOP1_NR_CLK 9 + +/* CCORE */ +#define PCLK_RTC 1 +#define CCORE_NR_CLK 2 + +/* PERIC0 */ +#define PCLK_UART0 1 +#define SCLK_UART0 2 +#define PCLK_HSI2C0 3 +#define PCLK_HSI2C1 4 +#define PCLK_HSI2C4 5 +#define PCLK_HSI2C5 6 +#define PCLK_HSI2C9 7 +#define PCLK_HSI2C10 8 +#define PCLK_HSI2C11 9 +#define PCLK_PWM 10 +#define SCLK_PWM 11 +#define PCLK_ADCIF 12 +#define PERIC0_NR_CLK 13 + +/* PERIC1 */ +#define PCLK_UART1 1 +#define PCLK_UART2 2 +#define PCLK_UART3 3 +#define SCLK_UART1 4 +#define SCLK_UART2 5 +#define SCLK_UART3 6 +#define PCLK_HSI2C2 7 +#define PCLK_HSI2C3 8 +#define PCLK_HSI2C6 9 +#define PCLK_HSI2C7 10 +#define PCLK_HSI2C8 11 +#define PERIC1_NR_CLK 12 + +/* PERIS */ +#define PCLK_CHIPID 1 +#define SCLK_CHIPID 2 +#define PCLK_WDT 3 +#define PCLK_TMU 4 +#define SCLK_TMU 5 +#define PERIS_NR_CLK 6 + +/* FSYS0 */ +#define ACLK_MMC2 1 +#define FSYS0_NR_CLK 2 + +/* FSYS1 */ +#define ACLK_MMC1 1 +#define ACLK_MMC0 2 +#define FSYS1_NR_CLK 3 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h new file mode 100644 index 000000000000..591f7fba89e2 --- /dev/null +++ b/include/dt-bindings/clock/marvell,mmp2.h @@ -0,0 +1,74 @@ +#ifndef __DTS_MARVELL_MMP2_CLOCK_H +#define __DTS_MARVELL_MMP2_CLOCK_H + +/* fixed clocks and plls */ +#define MMP2_CLK_CLK32 1 +#define MMP2_CLK_VCTCXO 2 +#define MMP2_CLK_PLL1 3 +#define MMP2_CLK_PLL1_2 8 +#define MMP2_CLK_PLL1_4 9 +#define MMP2_CLK_PLL1_8 10 +#define MMP2_CLK_PLL1_16 11 +#define MMP2_CLK_PLL1_3 12 +#define MMP2_CLK_PLL1_6 13 +#define MMP2_CLK_PLL1_12 14 +#define MMP2_CLK_PLL1_20 15 +#define MMP2_CLK_PLL2 16 +#define MMP2_CLK_PLL2_2 17 +#define MMP2_CLK_PLL2_4 18 +#define MMP2_CLK_PLL2_8 19 +#define MMP2_CLK_PLL2_16 20 +#define MMP2_CLK_PLL2_3 21 +#define MMP2_CLK_PLL2_6 22 +#define MMP2_CLK_PLL2_12 23 +#define MMP2_CLK_VCTCXO_2 24 +#define MMP2_CLK_VCTCXO_4 25 +#define MMP2_CLK_UART_PLL 26 +#define MMP2_CLK_USB_PLL 27 + +/* apb periphrals */ +#define MMP2_CLK_TWSI0 60 +#define MMP2_CLK_TWSI1 61 +#define MMP2_CLK_TWSI2 62 +#define MMP2_CLK_TWSI3 63 +#define MMP2_CLK_TWSI4 64 +#define MMP2_CLK_TWSI5 65 +#define MMP2_CLK_GPIO 66 +#define MMP2_CLK_KPC 67 +#define MMP2_CLK_RTC 68 +#define MMP2_CLK_PWM0 69 +#define MMP2_CLK_PWM1 70 +#define MMP2_CLK_PWM2 71 +#define MMP2_CLK_PWM3 72 +#define MMP2_CLK_UART0 73 +#define MMP2_CLK_UART1 74 +#define MMP2_CLK_UART2 75 +#define MMP2_CLK_UART3 76 +#define MMP2_CLK_SSP0 77 +#define MMP2_CLK_SSP1 78 +#define MMP2_CLK_SSP2 79 +#define MMP2_CLK_SSP3 80 + +/* axi periphrals */ +#define MMP2_CLK_SDH0 101 +#define MMP2_CLK_SDH1 102 +#define MMP2_CLK_SDH2 103 +#define MMP2_CLK_SDH3 104 +#define MMP2_CLK_USB 105 +#define MMP2_CLK_DISP0 106 +#define MMP2_CLK_DISP0_MUX 107 +#define MMP2_CLK_DISP0_SPHY 108 +#define MMP2_CLK_DISP1 109 +#define MMP2_CLK_DISP1_MUX 110 +#define MMP2_CLK_CCIC_ARBITER 111 +#define MMP2_CLK_CCIC0 112 +#define MMP2_CLK_CCIC0_MIX 113 +#define MMP2_CLK_CCIC0_PHY 114 +#define MMP2_CLK_CCIC0_SPHY 115 +#define MMP2_CLK_CCIC1 116 +#define MMP2_CLK_CCIC1_MIX 117 +#define MMP2_CLK_CCIC1_PHY 118 +#define MMP2_CLK_CCIC1_SPHY 119 + +#define MMP2_NR_CLKS 200 +#endif diff --git a/include/dt-bindings/clock/marvell,pxa168.h b/include/dt-bindings/clock/marvell,pxa168.h new file mode 100644 index 000000000000..79630b9d74b8 --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa168.h @@ -0,0 +1,57 @@ +#ifndef __DTS_MARVELL_PXA168_CLOCK_H +#define __DTS_MARVELL_PXA168_CLOCK_H + +/* fixed clocks and plls */ +#define PXA168_CLK_CLK32 1 +#define PXA168_CLK_VCTCXO 2 +#define PXA168_CLK_PLL1 3 +#define PXA168_CLK_PLL1_2 8 +#define PXA168_CLK_PLL1_4 9 +#define PXA168_CLK_PLL1_8 10 +#define PXA168_CLK_PLL1_16 11 +#define PXA168_CLK_PLL1_6 12 +#define PXA168_CLK_PLL1_12 13 +#define PXA168_CLK_PLL1_24 14 +#define PXA168_CLK_PLL1_48 15 +#define PXA168_CLK_PLL1_96 16 +#define PXA168_CLK_PLL1_13 17 +#define PXA168_CLK_PLL1_13_1_5 18 +#define PXA168_CLK_PLL1_2_1_5 19 +#define PXA168_CLK_PLL1_3_16 20 +#define PXA168_CLK_UART_PLL 27 + +/* apb periphrals */ +#define PXA168_CLK_TWSI0 60 +#define PXA168_CLK_TWSI1 61 +#define PXA168_CLK_TWSI2 62 +#define PXA168_CLK_TWSI3 63 +#define PXA168_CLK_GPIO 64 +#define PXA168_CLK_KPC 65 +#define PXA168_CLK_RTC 66 +#define PXA168_CLK_PWM0 67 +#define PXA168_CLK_PWM1 68 +#define PXA168_CLK_PWM2 69 +#define PXA168_CLK_PWM3 70 +#define PXA168_CLK_UART0 71 +#define PXA168_CLK_UART1 72 +#define PXA168_CLK_UART2 73 +#define PXA168_CLK_SSP0 74 +#define PXA168_CLK_SSP1 75 +#define PXA168_CLK_SSP2 76 +#define PXA168_CLK_SSP3 77 +#define PXA168_CLK_SSP4 78 + +/* axi periphrals */ +#define PXA168_CLK_DFC 100 +#define PXA168_CLK_SDH0 101 +#define PXA168_CLK_SDH1 102 +#define PXA168_CLK_SDH2 103 +#define PXA168_CLK_USB 104 +#define PXA168_CLK_SPH 105 +#define PXA168_CLK_DISP0 106 +#define PXA168_CLK_CCIC0 107 +#define PXA168_CLK_CCIC0_PHY 108 +#define PXA168_CLK_CCIC0_SPHY 109 + +#define PXA168_NR_CLKS 200 +#endif diff --git a/include/dt-bindings/clock/marvell,pxa910.h b/include/dt-bindings/clock/marvell,pxa910.h new file mode 100644 index 000000000000..719cffb2bea2 --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa910.h @@ -0,0 +1,54 @@ +#ifndef __DTS_MARVELL_PXA910_CLOCK_H +#define __DTS_MARVELL_PXA910_CLOCK_H + +/* fixed clocks and plls */ +#define PXA910_CLK_CLK32 1 +#define PXA910_CLK_VCTCXO 2 +#define PXA910_CLK_PLL1 3 +#define PXA910_CLK_PLL1_2 8 +#define PXA910_CLK_PLL1_4 9 +#define PXA910_CLK_PLL1_8 10 +#define PXA910_CLK_PLL1_16 11 +#define PXA910_CLK_PLL1_6 12 +#define PXA910_CLK_PLL1_12 13 +#define PXA910_CLK_PLL1_24 14 +#define PXA910_CLK_PLL1_48 15 +#define PXA910_CLK_PLL1_96 16 +#define PXA910_CLK_PLL1_13 17 +#define PXA910_CLK_PLL1_13_1_5 18 +#define PXA910_CLK_PLL1_2_1_5 19 +#define PXA910_CLK_PLL1_3_16 20 +#define PXA910_CLK_UART_PLL 27 + +/* apb periphrals */ +#define PXA910_CLK_TWSI0 60 +#define PXA910_CLK_TWSI1 61 +#define PXA910_CLK_TWSI2 62 +#define PXA910_CLK_TWSI3 63 +#define PXA910_CLK_GPIO 64 +#define PXA910_CLK_KPC 65 +#define PXA910_CLK_RTC 66 +#define PXA910_CLK_PWM0 67 +#define PXA910_CLK_PWM1 68 +#define PXA910_CLK_PWM2 69 +#define PXA910_CLK_PWM3 70 +#define PXA910_CLK_UART0 71 +#define PXA910_CLK_UART1 72 +#define PXA910_CLK_UART2 73 +#define PXA910_CLK_SSP0 74 +#define PXA910_CLK_SSP1 75 + +/* axi periphrals */ +#define PXA910_CLK_DFC 100 +#define PXA910_CLK_SDH0 101 +#define PXA910_CLK_SDH1 102 +#define PXA910_CLK_SDH2 103 +#define PXA910_CLK_USB 104 +#define PXA910_CLK_SPH 105 +#define PXA910_CLK_DISP0 106 +#define PXA910_CLK_CCIC0 107 +#define PXA910_CLK_CCIC0_PHY 108 +#define PXA910_CLK_CCIC0_SPHY 109 + +#define PXA910_NR_CLKS 200 +#endif diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 100a08c47692..f60ce72a2b2c 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -71,6 +71,15 @@ #define SCLK_HDMI_CEC 110 #define SCLK_HEVC_CABAC 111 #define SCLK_HEVC_CORE 112 +#define SCLK_I2S0_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_SDIO1_DRV 116 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_SDIO1_SAMPLE 120 +#define SCLK_EMMC_SAMPLE 121 #define DCLK_VOP0 190 #define DCLK_VOP1 191 @@ -141,6 +150,10 @@ #define PCLK_VIO2_H2P 361 #define PCLK_CPU 362 #define PCLK_PERI 363 +#define PCLK_DDRUPCTL0 364 +#define PCLK_PUBL0 365 +#define PCLK_DDRUPCTL1 366 +#define PCLK_PUBL1 367 /* hclk gates */ #define HCLK_GPS 448 diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h index e835037a77b4..ab6cbba45401 100644 --- a/include/dt-bindings/dma/at91.h +++ b/include/dt-bindings/dma/at91.h @@ -9,6 +9,8 @@ #ifndef __DT_BINDINGS_AT91_DMA_H__ #define __DT_BINDINGS_AT91_DMA_H__ +/* ---------- HDMAC ---------- */ + /* * Source and/or destination peripheral ID */ @@ -24,4 +26,27 @@ #define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ #define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ + +/* ---------- XDMAC ---------- */ +#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) +#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) +#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ + << AT91_XDMAC_DT_MEM_IF_OFFSET) +#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ + & AT91_XDMAC_DT_MEM_IF_MASK) + +#define AT91_XDMAC_DT_PER_IF_MASK (0x1) +#define AT91_XDMAC_DT_PER_IF_OFFSET (14) +#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ + << AT91_XDMAC_DT_PER_IF_OFFSET) +#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ + & AT91_XDMAC_DT_PER_IF_MASK) + +#define AT91_XDMAC_DT_PERID_MASK (0x7f) +#define AT91_XDMAC_DT_PERID_OFFSET (24) +#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ + << AT91_XDMAC_DT_PERID_OFFSET) +#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ + & AT91_XDMAC_DT_PERID_MASK) + #endif /* __DT_BINDINGS_AT91_DMA_H__ */ diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index 1ea1b702fec2..d4110d5caa3e 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -7,14 +7,14 @@ #include <dt-bindings/interrupt-controller/irq.h> -/* interrupt specific cell 0 */ +/* interrupt specifier cell 0 */ #define GIC_SPI 0 #define GIC_PPI 1 /* * Interrupt specifier cell 2. - * The flaggs in irq.h are valid, plus those below. + * The flags in irq.h are valid, plus those below. */ #define GIC_CPU_MASK_RAW(x) ((x) << 8) #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h new file mode 100644 index 000000000000..cf35a577e371 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/mips-gic.h @@ -0,0 +1,9 @@ +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H + +#include <dt-bindings/interrupt-controller/irq.h> + +#define GIC_SHARED 0 +#define GIC_LOCAL 1 + +#endif diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h new file mode 100644 index 000000000000..6c901930eb3e --- /dev/null +++ b/include/dt-bindings/phy/phy.h @@ -0,0 +1,19 @@ +/* + * + * This header provides constants for the phy framework + * + * Copyright (C) 2014 STMicroelectronics + * Author: Gabriel Fernandez <gabriel.fernandez@st.com> + * License terms: GNU General Public License (GPL), version 2 + */ + +#ifndef _DT_BINDINGS_PHY +#define _DT_BINDINGS_PHY + +#define PHY_NONE 0 +#define PHY_TYPE_SATA 1 +#define PHY_TYPE_PCIE 2 +#define PHY_TYPE_USB2 3 +#define PHY_TYPE_USB3 4 + +#endif /* _DT_BINDINGS_PHY */ diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h new file mode 100644 index 000000000000..fa74d7cc960c --- /dev/null +++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h @@ -0,0 +1,142 @@ +/* + * This header provides constants for the Qualcomm PMIC GPIO binding. + */ + +#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H +#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H + +#define PMIC_GPIO_PULL_UP_30 0 +#define PMIC_GPIO_PULL_UP_1P5 1 +#define PMIC_GPIO_PULL_UP_31P5 2 +#define PMIC_GPIO_PULL_UP_1P5_30 3 + +#define PMIC_GPIO_STRENGTH_NO 0 +#define PMIC_GPIO_STRENGTH_HIGH 1 +#define PMIC_GPIO_STRENGTH_MED 2 +#define PMIC_GPIO_STRENGTH_LOW 3 + +/* + * Note: PM8018 GPIO3 and GPIO4 are supporting + * only S3 and L2 options (1.8V) + */ +#define PM8018_GPIO_L6 0 +#define PM8018_GPIO_L5 1 +#define PM8018_GPIO_S3 2 +#define PM8018_GPIO_L14 3 +#define PM8018_GPIO_L2 4 +#define PM8018_GPIO_L4 5 +#define PM8018_GPIO_VDD 6 + +/* + * Note: PM8038 GPIO7 and GPIO8 are supporting + * only L11 and L4 options (1.8V) + */ +#define PM8038_GPIO_VPH 0 +#define PM8038_GPIO_BB 1 +#define PM8038_GPIO_L11 2 +#define PM8038_GPIO_L15 3 +#define PM8038_GPIO_L4 4 +#define PM8038_GPIO_L3 5 +#define PM8038_GPIO_L17 6 + +#define PM8058_GPIO_VPH 0 +#define PM8058_GPIO_BB 1 +#define PM8058_GPIO_S3 2 +#define PM8058_GPIO_L3 3 +#define PM8058_GPIO_L7 4 +#define PM8058_GPIO_L6 5 +#define PM8058_GPIO_L5 6 +#define PM8058_GPIO_L2 7 + +#define PM8917_GPIO_VPH 0 +#define PM8917_GPIO_S4 2 +#define PM8917_GPIO_L15 3 +#define PM8917_GPIO_L4 4 +#define PM8917_GPIO_L3 5 +#define PM8917_GPIO_L17 6 + +#define PM8921_GPIO_VPH 0 +#define PM8921_GPIO_BB 1 +#define PM8921_GPIO_S4 2 +#define PM8921_GPIO_L15 3 +#define PM8921_GPIO_L4 4 +#define PM8921_GPIO_L3 5 +#define PM8921_GPIO_L17 6 + +/* + * Note: PM8941 gpios from 15 to 18 are supporting + * only S3 and L6 options (1.8V) + */ +#define PM8941_GPIO_VPH 0 +#define PM8941_GPIO_L1 1 +#define PM8941_GPIO_S3 2 +#define PM8941_GPIO_L6 3 + +/* + * Note: PMA8084 gpios from 15 to 18 are supporting + * only S4 and L6 options (1.8V) + */ +#define PMA8084_GPIO_VPH 0 +#define PMA8084_GPIO_L1 1 +#define PMA8084_GPIO_S4 2 +#define PMA8084_GPIO_L6 3 + +/* To be used with "function" */ +#define PMIC_GPIO_FUNC_NORMAL "normal" +#define PMIC_GPIO_FUNC_PAIRED "paired" +#define PMIC_GPIO_FUNC_FUNC1 "func1" +#define PMIC_GPIO_FUNC_FUNC2 "func2" +#define PMIC_GPIO_FUNC_DTEST1 "dtest1" +#define PMIC_GPIO_FUNC_DTEST2 "dtest2" +#define PMIC_GPIO_FUNC_DTEST3 "dtest3" +#define PMIC_GPIO_FUNC_DTEST4 "dtest4" + +#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2 + +#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2 +#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1 + +#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2 +#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2 + +#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 +#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1 +#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2 + +#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1 +#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2 +#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1 +#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2 +#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1 + +#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h new file mode 100644 index 000000000000..d2c7dabe3223 --- /dev/null +++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h @@ -0,0 +1,44 @@ +/* + * This header provides constants for the Qualcomm PMIC's + * Multi-Purpose Pin binding. + */ + +#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H +#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H + +/* power-source */ +#define PM8841_MPP_VPH 0 +#define PM8841_MPP_S3 2 + +#define PM8941_MPP_VPH 0 +#define PM8941_MPP_L1 1 +#define PM8941_MPP_S3 2 +#define PM8941_MPP_L6 3 + +#define PMA8084_MPP_VPH 0 +#define PMA8084_MPP_L1 1 +#define PMA8084_MPP_S4 2 +#define PMA8084_MPP_L6 3 + +/* + * Analog Input - Set the source for analog input. + * To be used with "qcom,amux-route" property + */ +#define PMIC_MPP_AMUX_ROUTE_CH5 0 +#define PMIC_MPP_AMUX_ROUTE_CH6 1 +#define PMIC_MPP_AMUX_ROUTE_CH7 2 +#define PMIC_MPP_AMUX_ROUTE_CH8 3 +#define PMIC_MPP_AMUX_ROUTE_ABUS1 4 +#define PMIC_MPP_AMUX_ROUTE_ABUS2 5 +#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 +#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 + +/* To be used with "function" */ +#define PMIC_MPP_FUNC_NORMAL "normal" +#define PMIC_MPP_FUNC_PAIRED "paired" +#define PMIC_MPP_FUNC_DTEST1 "dtest1" +#define PMIC_MPP_FUNC_DTEST2 "dtest2" +#define PMIC_MPP_FUNC_DTEST3 "dtest3" +#define PMIC_MPP_FUNC_DTEST4 "dtest4" + +#endif diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h new file mode 100644 index 000000000000..85aaf66690f9 --- /dev/null +++ b/include/dt-bindings/thermal/tegra124-soctherm.h @@ -0,0 +1,13 @@ +/* + * This header provides constants for binding nvidia,tegra124-soctherm. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H +#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H + +#define TEGRA124_SOCTHERM_SENSOR_CPU 0 +#define TEGRA124_SOCTHERM_SENSOR_MEM 1 +#define TEGRA124_SOCTHERM_SENSOR_GPU 2 +#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 + +#endif diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h index 59822a995858..b5e6b0069ac7 100644 --- a/include/dt-bindings/thermal/thermal.h +++ b/include/dt-bindings/thermal/thermal.h @@ -11,7 +11,7 @@ #define _DT_BINDINGS_THERMAL_THERMAL_H /* On cooling devices upper and lower limits */ -#define THERMAL_NO_LIMIT (-1UL) +#define THERMAL_NO_LIMIT (~0) #endif |
