diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/gpio/meson-a1-gpio.h | 73 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,msm8974.h | 146 | ||||
| -rw-r--r-- | include/dt-bindings/net/qca-ar803x.h | 13 | ||||
| -rw-r--r-- | include/dt-bindings/net/ti-dp83869.h | 42 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/at91.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/pmu/exynos_ppmu.h | 25 | ||||
| -rw-r--r-- | include/dt-bindings/regulator/dlg,da9063-regulator.h | 16 | ||||
| -rw-r--r-- | include/dt-bindings/sound/samsung-i2s.h | 12 |
8 files changed, 326 insertions, 5 deletions
diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h new file mode 100644 index 000000000000..40e57a5ff1db --- /dev/null +++ b/include/dt-bindings/gpio/meson-a1-gpio.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_A1_GPIO_H +#define _DT_BINDINGS_MESON_A1_GPIO_H + +#define GPIOP_0 0 +#define GPIOP_1 1 +#define GPIOP_2 2 +#define GPIOP_3 3 +#define GPIOP_4 4 +#define GPIOP_5 5 +#define GPIOP_6 6 +#define GPIOP_7 7 +#define GPIOP_8 8 +#define GPIOP_9 9 +#define GPIOP_10 10 +#define GPIOP_11 11 +#define GPIOP_12 12 +#define GPIOB_0 13 +#define GPIOB_1 14 +#define GPIOB_2 15 +#define GPIOB_3 16 +#define GPIOB_4 17 +#define GPIOB_5 18 +#define GPIOB_6 19 +#define GPIOX_0 20 +#define GPIOX_1 21 +#define GPIOX_2 22 +#define GPIOX_3 23 +#define GPIOX_4 24 +#define GPIOX_5 25 +#define GPIOX_6 26 +#define GPIOX_7 27 +#define GPIOX_8 28 +#define GPIOX_9 29 +#define GPIOX_10 30 +#define GPIOX_11 31 +#define GPIOX_12 32 +#define GPIOX_13 33 +#define GPIOX_14 34 +#define GPIOX_15 35 +#define GPIOX_16 36 +#define GPIOF_0 37 +#define GPIOF_1 38 +#define GPIOF_2 39 +#define GPIOF_3 40 +#define GPIOF_4 41 +#define GPIOF_5 42 +#define GPIOF_6 43 +#define GPIOF_7 44 +#define GPIOF_8 45 +#define GPIOF_9 46 +#define GPIOF_10 47 +#define GPIOF_11 48 +#define GPIOF_12 49 +#define GPIOA_0 50 +#define GPIOA_1 51 +#define GPIOA_2 52 +#define GPIOA_3 53 +#define GPIOA_4 54 +#define GPIOA_5 55 +#define GPIOA_6 56 +#define GPIOA_7 57 +#define GPIOA_8 58 +#define GPIOA_9 59 +#define GPIOA_10 60 +#define GPIOA_11 61 + +#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/interconnect/qcom,msm8974.h b/include/dt-bindings/interconnect/qcom,msm8974.h new file mode 100644 index 000000000000..e65ae27ffff2 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,msm8974.h @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Qualcomm msm8974 interconnect IDs + * + * Copyright (c) 2019 Brian Masney <masneyb@onstation.org> + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8974_H + +#define BIMC_MAS_AMPSS_M0 0 +#define BIMC_MAS_AMPSS_M1 1 +#define BIMC_MAS_MSS_PROC 2 +#define BIMC_TO_MNOC 3 +#define BIMC_TO_SNOC 4 +#define BIMC_SLV_EBI_CH0 5 +#define BIMC_SLV_AMPSS_L2 6 + +#define CNOC_MAS_RPM_INST 0 +#define CNOC_MAS_RPM_DATA 1 +#define CNOC_MAS_RPM_SYS 2 +#define CNOC_MAS_DEHR 3 +#define CNOC_MAS_QDSS_DAP 4 +#define CNOC_MAS_SPDM 5 +#define CNOC_MAS_TIC 6 +#define CNOC_SLV_CLK_CTL 7 +#define CNOC_SLV_CNOC_MSS 8 +#define CNOC_SLV_SECURITY 9 +#define CNOC_SLV_TCSR 10 +#define CNOC_SLV_TLMM 11 +#define CNOC_SLV_CRYPTO_0_CFG 12 +#define CNOC_SLV_CRYPTO_1_CFG 13 +#define CNOC_SLV_IMEM_CFG 14 +#define CNOC_SLV_MESSAGE_RAM 15 +#define CNOC_SLV_BIMC_CFG 16 +#define CNOC_SLV_BOOT_ROM 17 +#define CNOC_SLV_PMIC_ARB 18 +#define CNOC_SLV_SPDM_WRAPPER 19 +#define CNOC_SLV_DEHR_CFG 20 +#define CNOC_SLV_MPM 21 +#define CNOC_SLV_QDSS_CFG 22 +#define CNOC_SLV_RBCPR_CFG 23 +#define CNOC_SLV_RBCPR_QDSS_APU_CFG 24 +#define CNOC_TO_SNOC 25 +#define CNOC_SLV_CNOC_ONOC_CFG 26 +#define CNOC_SLV_CNOC_MNOC_MMSS_CFG 27 +#define CNOC_SLV_CNOC_MNOC_CFG 28 +#define CNOC_SLV_PNOC_CFG 29 +#define CNOC_SLV_SNOC_MPU_CFG 30 +#define CNOC_SLV_SNOC_CFG 31 +#define CNOC_SLV_EBI1_DLL_CFG 32 +#define CNOC_SLV_PHY_APU_CFG 33 +#define CNOC_SLV_EBI1_PHY_CFG 34 +#define CNOC_SLV_RPM 35 +#define CNOC_SLV_SERVICE_CNOC 36 + +#define MNOC_MAS_GRAPHICS_3D 0 +#define MNOC_MAS_JPEG 1 +#define MNOC_MAS_MDP_PORT0 2 +#define MNOC_MAS_VIDEO_P0 3 +#define MNOC_MAS_VIDEO_P1 4 +#define MNOC_MAS_VFE 5 +#define MNOC_TO_CNOC 6 +#define MNOC_TO_BIMC 7 +#define MNOC_SLV_CAMERA_CFG 8 +#define MNOC_SLV_DISPLAY_CFG 9 +#define MNOC_SLV_OCMEM_CFG 10 +#define MNOC_SLV_CPR_CFG 11 +#define MNOC_SLV_CPR_XPU_CFG 12 +#define MNOC_SLV_MISC_CFG 13 +#define MNOC_SLV_MISC_XPU_CFG 14 +#define MNOC_SLV_VENUS_CFG 15 +#define MNOC_SLV_GRAPHICS_3D_CFG 16 +#define MNOC_SLV_MMSS_CLK_CFG 17 +#define MNOC_SLV_MMSS_CLK_XPU_CFG 18 +#define MNOC_SLV_MNOC_MPU_CFG 19 +#define MNOC_SLV_ONOC_MPU_CFG 20 +#define MNOC_SLV_SERVICE_MNOC 21 + +#define OCMEM_NOC_TO_OCMEM_VNOC 0 +#define OCMEM_MAS_JPEG_OCMEM 1 +#define OCMEM_MAS_MDP_OCMEM 2 +#define OCMEM_MAS_VIDEO_P0_OCMEM 3 +#define OCMEM_MAS_VIDEO_P1_OCMEM 4 +#define OCMEM_MAS_VFE_OCMEM 5 +#define OCMEM_MAS_CNOC_ONOC_CFG 6 +#define OCMEM_SLV_SERVICE_ONOC 7 +#define OCMEM_VNOC_TO_SNOC 8 +#define OCMEM_VNOC_TO_OCMEM_NOC 9 +#define OCMEM_VNOC_MAS_GFX3D 10 +#define OCMEM_SLV_OCMEM 11 + +#define PNOC_MAS_PNOC_CFG 0 +#define PNOC_MAS_SDCC_1 1 +#define PNOC_MAS_SDCC_3 2 +#define PNOC_MAS_SDCC_4 3 +#define PNOC_MAS_SDCC_2 4 +#define PNOC_MAS_TSIF 5 +#define PNOC_MAS_BAM_DMA 6 +#define PNOC_MAS_BLSP_2 7 +#define PNOC_MAS_USB_HSIC 8 +#define PNOC_MAS_BLSP_1 9 +#define PNOC_MAS_USB_HS 10 +#define PNOC_TO_SNOC 11 +#define PNOC_SLV_SDCC_1 12 +#define PNOC_SLV_SDCC_3 13 +#define PNOC_SLV_SDCC_2 14 +#define PNOC_SLV_SDCC_4 15 +#define PNOC_SLV_TSIF 16 +#define PNOC_SLV_BAM_DMA 17 +#define PNOC_SLV_BLSP_2 18 +#define PNOC_SLV_USB_HSIC 19 +#define PNOC_SLV_BLSP_1 20 +#define PNOC_SLV_USB_HS 21 +#define PNOC_SLV_PDM 22 +#define PNOC_SLV_PERIPH_APU_CFG 23 +#define PNOC_SLV_PNOC_MPU_CFG 24 +#define PNOC_SLV_PRNG 25 +#define PNOC_SLV_SERVICE_PNOC 26 + +#define SNOC_MAS_LPASS_AHB 0 +#define SNOC_MAS_QDSS_BAM 1 +#define SNOC_MAS_SNOC_CFG 2 +#define SNOC_TO_BIMC 3 +#define SNOC_TO_CNOC 4 +#define SNOC_TO_PNOC 5 +#define SNOC_TO_OCMEM_VNOC 6 +#define SNOC_MAS_CRYPTO_CORE0 7 +#define SNOC_MAS_CRYPTO_CORE1 8 +#define SNOC_MAS_LPASS_PROC 9 +#define SNOC_MAS_MSS 10 +#define SNOC_MAS_MSS_NAV 11 +#define SNOC_MAS_OCMEM_DMA 12 +#define SNOC_MAS_WCSS 13 +#define SNOC_MAS_QDSS_ETR 14 +#define SNOC_MAS_USB3 15 +#define SNOC_SLV_AMPSS 16 +#define SNOC_SLV_LPASS 17 +#define SNOC_SLV_USB3 18 +#define SNOC_SLV_WCSS 19 +#define SNOC_SLV_OCIMEM 20 +#define SNOC_SLV_SNOC_OCMEM 21 +#define SNOC_SLV_SERVICE_SNOC 22 +#define SNOC_SLV_QDSS_STM 23 + +#endif diff --git a/include/dt-bindings/net/qca-ar803x.h b/include/dt-bindings/net/qca-ar803x.h new file mode 100644 index 000000000000..9c046c7242ed --- /dev/null +++ b/include/dt-bindings/net/qca-ar803x.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Qualcomm Atheros AR803x PHYs + */ + +#ifndef _DT_BINDINGS_QCA_AR803X_H +#define _DT_BINDINGS_QCA_AR803X_H + +#define AR803X_STRENGTH_FULL 0 +#define AR803X_STRENGTH_HALF 1 +#define AR803X_STRENGTH_QUARTER 2 + +#endif diff --git a/include/dt-bindings/net/ti-dp83869.h b/include/dt-bindings/net/ti-dp83869.h new file mode 100644 index 000000000000..218b1a64e975 --- /dev/null +++ b/include/dt-bindings/net/ti-dp83869.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Device Tree constants for the Texas Instruments DP83869 PHY + * + * Author: Dan Murphy <dmurphy@ti.com> + * + * Copyright: (C) 2019 Texas Instruments, Inc. + */ + +#ifndef _DT_BINDINGS_TI_DP83869_H +#define _DT_BINDINGS_TI_DP83869_H + +/* PHY CTRL bits */ +#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* IO_MUX_CFG - Clock output selection */ +#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0 +#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1 +#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2 +#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3 +#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 +#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 +#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 +#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 +#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8 +#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9 +#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa +#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb +#define DP83869_CLK_O_SEL_REF_CLK 0xc + +#define DP83869_RGMII_COPPER_ETHERNET 0x00 +#define DP83869_RGMII_1000_BASE 0x01 +#define DP83869_RGMII_100_BASE 0x02 +#define DP83869_RGMII_SGMII_BRIDGE 0x03 +#define DP83869_1000M_MEDIA_CONVERT 0x04 +#define DP83869_100M_MEDIA_CONVERT 0x05 +#define DP83869_SGMII_COPPER_ETHERNET 0x06 + +#endif diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h index 3831f91fb3ba..e8e117306b1b 100644 --- a/include/dt-bindings/pinctrl/at91.h +++ b/include/dt-bindings/pinctrl/at91.h @@ -27,8 +27,8 @@ #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) #define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) -#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9) -#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9) +#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9) +#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9) #define AT91_PIOA 0 #define AT91_PIOB 1 diff --git a/include/dt-bindings/pmu/exynos_ppmu.h b/include/dt-bindings/pmu/exynos_ppmu.h new file mode 100644 index 000000000000..8724abe130f3 --- /dev/null +++ b/include/dt-bindings/pmu/exynos_ppmu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos PPMU event types for counting in regs + * + * Copyright (c) 2019, Samsung Electronics + * Author: Lukasz Luba <l.luba@partner.samsung.com> + */ + +#ifndef __DT_BINDINGS_PMU_EXYNOS_PPMU_H +#define __DT_BINDINGS_PMU_EXYNOS_PPMU_H + +#define PPMU_RO_BUSY_CYCLE_CNT 0x0 +#define PPMU_WO_BUSY_CYCLE_CNT 0x1 +#define PPMU_RW_BUSY_CYCLE_CNT 0x2 +#define PPMU_RO_REQUEST_CNT 0x3 +#define PPMU_WO_REQUEST_CNT 0x4 +#define PPMU_RO_DATA_CNT 0x5 +#define PPMU_WO_DATA_CNT 0x6 +#define PPMU_RO_LATENCY 0x12 +#define PPMU_WO_LATENCY 0x16 +#define PPMU_V2_RO_DATA_CNT 0x4 +#define PPMU_V2_WO_DATA_CNT 0x5 +#define PPMU_V2_EVT3_RW_DATA_CNT 0x22 + +#endif diff --git a/include/dt-bindings/regulator/dlg,da9063-regulator.h b/include/dt-bindings/regulator/dlg,da9063-regulator.h new file mode 100644 index 000000000000..1de710dd0899 --- /dev/null +++ b/include/dt-bindings/regulator/dlg,da9063-regulator.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H +#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H + +/* + * These buck mode constants may be used to specify values in device tree + * properties (e.g. regulator-initial-mode). + * A description of the following modes is in the manufacturers datasheet. + */ + +#define DA9063_BUCK_MODE_SLEEP 1 +#define DA9063_BUCK_MODE_SYNC 2 +#define DA9063_BUCK_MODE_AUTO 3 + +#endif diff --git a/include/dt-bindings/sound/samsung-i2s.h b/include/dt-bindings/sound/samsung-i2s.h index 77545f14c379..250de0d6c734 100644 --- a/include/dt-bindings/sound/samsung-i2s.h +++ b/include/dt-bindings/sound/samsung-i2s.h @@ -2,8 +2,14 @@ #ifndef _DT_BINDINGS_SAMSUNG_I2S_H #define _DT_BINDINGS_SAMSUNG_I2S_H -#define CLK_I2S_CDCLK 0 -#define CLK_I2S_RCLK_SRC 1 -#define CLK_I2S_RCLK_PSR 2 +#define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ + +#define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to + * RCLKSRC bit in IISMOD register) + */ + +#define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock + * (corresponding to the IISPSR register) + */ #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ |
