diff options
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-ixp2000/gpio.h | 31 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp2000/io.h | 96 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp2000/ixdp2x00.h | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp2000/ixdp2x01.h | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp2000/ixp2000-regs.h | 21 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp2000/platform.h | 22 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp2000/vmalloc.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp4xx/debug-macro.S | 1 | ||||
| -rw-r--r-- | include/asm-arm/arch-ixp4xx/ixp4xx-regs.h | 10 | ||||
| -rw-r--r-- | include/asm-arm/arch-omap/usb.h | 9 | ||||
| -rw-r--r-- | include/asm-arm/arch-pxa/debug-macro.S | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-s3c2410/audio.h | 49 | ||||
| -rw-r--r-- | include/asm-arm/hardware/arm_timer.h | 21 | ||||
| -rw-r--r-- | include/asm-arm/ide.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/io.h | 4 | ||||
| -rw-r--r-- | include/asm-arm/mach/time.h | 23 | ||||
| -rw-r--r-- | include/asm-arm/pci.h | 10 | ||||
| -rw-r--r-- | include/asm-arm/signal.h | 1 | ||||
| -rw-r--r-- | include/asm-arm/system.h | 42 | ||||
| -rw-r--r-- | include/asm-arm/tlbflush.h | 28 |
20 files changed, 291 insertions, 91 deletions
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h index 84634af5cc64..03cbbe1fd9d8 100644 --- a/include/asm-arm/arch-ixp2000/gpio.h +++ b/include/asm-arm/arch-ixp2000/gpio.h @@ -1,5 +1,5 @@ /* - * include/asm-arm/arch-ixp2000/ixp2000-gpio.h + * include/asm-arm/arch-ixp2000/gpio.h * * Copyright (C) 2002 Intel Corporation. * @@ -16,26 +16,18 @@ * Use this instead of directly setting the GPIO registers. * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb) */ -#ifndef _ASM_ARCH_IXP2000_GPIO_H_ -#define _ASM_ARCH_IXP2000_GPIO_H_ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H #ifndef __ASSEMBLY__ -#define GPIO_OUT 0x0 -#define GPIO_IN 0x80 + +#define GPIO_IN 0 +#define GPIO_OUT 1 #define IXP2000_GPIO_LOW 0 #define IXP2000_GPIO_HIGH 1 -#define GPIO_NO_EDGES 0 -#define GPIO_FALLING_EDGE 1 -#define GPIO_RISING_EDGE 2 -#define GPIO_BOTH_EDGES 3 -#define GPIO_LEVEL_LOW 4 -#define GPIO_LEVEL_HIGH 8 - -extern void set_GPIO_IRQ_edge(int gpio_nr, int edge); -extern void set_GPIO_IRQ_level(int gpio_nr, int level); -extern void gpio_line_config(int line, int style); +extern void gpio_line_config(int line, int direction); static inline int gpio_line_get(int line) { @@ -45,11 +37,12 @@ static inline int gpio_line_get(int line) static inline void gpio_line_set(int line, int value) { if (value == IXP2000_GPIO_HIGH) { - ixp_reg_write(IXP2000_GPIO_POSR, BIT(line)); - } else if (value == IXP2000_GPIO_LOW) - ixp_reg_write(IXP2000_GPIO_POCR, BIT(line)); + ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line); + } else if (value == IXP2000_GPIO_LOW) { + ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line); + } } #endif /* !__ASSEMBLY__ */ -#endif /* ASM_ARCH_IXP2000_GPIO_H_ */ +#endif /* ASM_ARCH_IXP2000_GPIO_H_ */ diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h index 083462668e18..3241cd6f0778 100644 --- a/include/asm-arm/arch-ixp2000/io.h +++ b/include/asm-arm/arch-ixp2000/io.h @@ -17,18 +17,23 @@ #define IO_SPACE_LIMIT 0xffffffff #define __mem_pci(a) (a) -#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) /* - * The IXP2400 before revision B0 asserts byte lanes for PCI I/O + * The A? revisions of the IXP2000s assert byte lanes for PCI I/O * transactions the other way round (MEM transactions don't have this - * issue), so we need to override the standard functions. B0 and later - * have a bit that can be set to 1 to get the 'proper' behavior, but - * since that isn't available on the A? revisions we just keep doing - * things manually. + * issue), so if we want to support those models, we need to override + * the standard I/O functions. + * + * B0 and later have a bit that can be set to 1 to get the proper + * behavior for I/O transactions, which then allows us to use the + * standard I/O functions. This is what we do if the user does not + * explicitly ask for support for pre-B0. */ -#define alignb(addr) (void __iomem *)((unsigned long)addr ^ 3) -#define alignw(addr) (void __iomem *)((unsigned long)addr ^ 2) +#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO +#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) + +#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3) +#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2) #define outb(v,p) __raw_writeb((v),alignb(___io(p))) #define outw(v,p) __raw_writew((v),alignw(___io(p))) @@ -48,6 +53,81 @@ #define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) #define insl(p,d,l) __raw_readsl(___io(p),d,l) +#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE) + +#define ioread8(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readb(alignb(p)); \ + } else { \ + __v = __raw_readb(p); \ + } \ + \ + __v; \ + }) \ + +#define ioread16(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readw(alignw(p)); \ + } else { \ + __v = le16_to_cpu(__raw_readw(p)); \ + } \ + \ + __v; \ + }) + +#define ioread32(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readl(p); \ + } else { \ + __v = le32_to_cpu(__raw_readl(p)); \ + } \ + \ + __v; \ + }) + +#define iowrite8(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writeb((v), alignb(p)); \ + } else { \ + __raw_writeb((v), p); \ + } \ + }) + +#define iowrite16(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writew((v), alignw(p)); \ + } else { \ + __raw_writew(cpu_to_le16(v), p); \ + } \ + }) + +#define iowrite32(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writel((v), p); \ + } else { \ + __raw_writel(cpu_to_le32(v), p); \ + } \ + }) + +#define ioport_map(port, nr) ___io(port) + +#define ioport_unmap(addr) +#else +#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) +#endif + #ifdef CONFIG_ARCH_IXDP2X01 /* diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h index 3a398dfbf125..229381c64283 100644 --- a/include/asm-arm/arch-ixp2000/ixdp2x00.h +++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h @@ -21,8 +21,8 @@ * On board CPLD memory map */ #define IXDP2X00_PHYS_CPLD_BASE 0xc7000000 -#define IXDP2X00_VIRT_CPLD_BASE 0xfafff000 -#define IXDP2X00_CPLD_SIZE 0x00001000 +#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000 +#define IXDP2X00_CPLD_SIZE 0x00100000 #define IXDP2X00_CPLD_REG(x) \ diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h index b3a1bcda8d01..b768009c3a51 100644 --- a/include/asm-arm/arch-ixp2000/ixdp2x01.h +++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h @@ -18,8 +18,8 @@ #define __IXDP2X01_H__ #define IXDP2X01_PHYS_CPLD_BASE 0xc6024000 -#define IXDP2X01_VIRT_CPLD_BASE 0xfafff000 -#define IXDP2X01_CPLD_REGION_SIZE 0x00001000 +#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000 +#define IXDP2X01_CPLD_REGION_SIZE 0x00100000 #define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg) #define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg) diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h index a1d9e181b10f..75623f81ef75 100644 --- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h +++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h @@ -18,6 +18,21 @@ #ifndef _IXP2000_REGS_H_ #define _IXP2000_REGS_H_ +/* + * IXP2000 linux memory map: + * + * virt phys size + * fb000000 db000000 16M PCI CFG1 + * fc000000 da000000 16M PCI CFG0 + * fd000000 d8000000 16M PCI I/O + * fe[0-7]00000 8M per-platform mappings + * feb00000 c8000000 1M MSF + * fec00000 df000000 1M PCI CSRs + * fed00000 de000000 1M PCI CREG + * fee00000 d6000000 1M INTCTL + * fef00000 c0000000 1M CAP + */ + /* * Static I/O regions. * @@ -71,6 +86,10 @@ #define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 #define IXP2000_PCI_CSR_SIZE 0x00100000 +#define IXP2000_MSF_PHYS_BASE 0xc8000000 +#define IXP2000_MSF_VIRT_BASE 0xfeb00000 +#define IXP2000_MSF_SIZE 0x00100000 + #define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 #define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 #define IXP2000_PCI_IO_SIZE 0x01000000 @@ -241,7 +260,7 @@ #define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ #define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ #define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ -#define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */ +#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */ #define IXP2000_PCI_RST_REL (1 << 2) #define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h index 901bba6d02b4..52ded516ea5c 100644 --- a/include/asm-arm/arch-ixp2000/platform.h +++ b/include/asm-arm/arch-ixp2000/platform.h @@ -138,30 +138,10 @@ struct ixp2000_flash_data { unsigned long (*bank_setup)(unsigned long); }; -/* - * GPIO helper functions - */ -#define GPIO_IN 0 -#define GPIO_OUT 1 - -extern void gpio_line_config(int line, int style); - -static inline int gpio_line_get(int line) -{ - return (((*IXP2000_GPIO_PLR) >> line) & 1); -} - -static inline void gpio_line_set(int line, int value) -{ - if (value) - ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line)); - else - ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line)); -} - struct ixp2000_i2c_pins { unsigned long sda_pin; unsigned long scl_pin; }; + #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h index 473dff4ec561..275136963a0c 100644 --- a/include/asm-arm/arch-ixp2000/vmalloc.h +++ b/include/asm-arm/arch-ixp2000/vmalloc.h @@ -17,4 +17,4 @@ * The vmalloc() routines leaves a hole of 4kB between each vmalloced * area for the same reason. ;) */ -#define VMALLOC_END 0xfaffefff +#define VMALLOC_END 0xfb000000 diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S index 4499ae8e4b44..2e23651e217f 100644 --- a/include/asm-arm/arch-ixp4xx/debug-macro.S +++ b/include/asm-arm/arch-ixp4xx/debug-macro.S @@ -15,6 +15,7 @@ tst \rx, #1 @ MMU enabled? moveq \rx, #0xc8000000 movne \rx, #0xff000000 + orrne \rx, \rx, #0x00b00000 add \rx,\rx,#3 @ Uart regs are at off set of 3 if @ byte writes used - Big Endian. .endm diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h index 8eeb1db6309d..004696a95bdb 100644 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h @@ -69,6 +69,16 @@ #define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000) #define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000) +/* + * Debug UART + * + * This is basically a remap of UART1 into a region that is section + * aligned so that it * can be used with the low-level debug code. + */ +#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000) +#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000) +#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000) + #define IXP4XX_EXP_CS0_OFFSET 0x00 #define IXP4XX_EXP_CS1_OFFSET 0x04 #define IXP4XX_EXP_CS2_OFFSET 0x08 diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h index 1438c6cef0ca..054fb9a8e0c6 100644 --- a/include/asm-arm/arch-omap/usb.h +++ b/include/asm-arm/arch-omap/usb.h @@ -47,6 +47,15 @@ # define HMC_TLLATTACH (1 << 6) # define OTG_HMC(w) (((w)>>0)&0x3f) #define OTG_CTRL_REG OTG_REG32(0x0c) +# define OTG_USB2_EN (1 << 29) +# define OTG_USB2_DP (1 << 28) +# define OTG_USB2_DM (1 << 27) +# define OTG_USB1_EN (1 << 26) +# define OTG_USB1_DP (1 << 25) +# define OTG_USB1_DM (1 << 24) +# define OTG_USB0_EN (1 << 23) +# define OTG_USB0_DP (1 << 22) +# define OTG_USB0_DM (1 << 21) # define OTG_ASESSVLD (1 << 20) # define OTG_BSESSEND (1 << 19) # define OTG_BSESSVLD (1 << 18) diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S index f288e74b67c2..b6ec68879176 100644 --- a/include/asm-arm/arch-pxa/debug-macro.S +++ b/include/asm-arm/arch-pxa/debug-macro.S @@ -11,6 +11,8 @@ * */ +#include "hardware.h" + .macro addruart,rx mrc p15, 0, \rx, c1, c0 tst \rx, #1 @ MMU enabled? diff --git a/include/asm-arm/arch-s3c2410/audio.h b/include/asm-arm/arch-s3c2410/audio.h new file mode 100644 index 000000000000..0d276e67f2fb --- /dev/null +++ b/include/asm-arm/arch-s3c2410/audio.h @@ -0,0 +1,49 @@ +/* linux/include/asm-arm/arch-s3c2410/audio.h + * + * (c) 2004-2005 Simtec Electronics + * http://www.simtec.co.uk/products/SWLINUX/ + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX - Audio platfrom_device info + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Changelog: + * 20-Nov-2004 BJD Created file + * 07-Mar-2005 BJD Added suspend/resume calls +*/ + +#ifndef __ASM_ARCH_AUDIO_H +#define __ASM_ARCH_AUDIO_H __FILE__ + +/* struct s3c24xx_iis_ops + * + * called from the s3c24xx audio core to deal with the architecture + * or the codec's setup and control. + * + * the pointer to itself is passed through in case the caller wants to + * embed this in an larger structure for easy reference to it's context. +*/ + +struct s3c24xx_iis_ops { + struct module *owner; + + int (*startup)(struct s3c24xx_iis_ops *me); + void (*shutdown)(struct s3c24xx_iis_ops *me); + int (*suspend)(struct s3c24xx_iis_ops *me); + int (*resume)(struct s3c24xx_iis_ops *me); + + int (*open)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm); + int (*close)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm); + int (*prepare)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm, snd_pcm_runtime_t *rt); +}; + +struct s3c24xx_platdata_iis { + const char *codec_clk; + struct s3c24xx_iis_ops *ops; + int (*match_dev)(struct device *dev); +}; + +#endif /* __ASM_ARCH_AUDIO_H */ diff --git a/include/asm-arm/hardware/arm_timer.h b/include/asm-arm/hardware/arm_timer.h new file mode 100644 index 000000000000..04be3bdf46b8 --- /dev/null +++ b/include/asm-arm/hardware/arm_timer.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H +#define __ASM_ARM_HARDWARE_ARM_TIMER_H + +#define TIMER_LOAD 0x00 +#define TIMER_VALUE 0x04 +#define TIMER_CTRL 0x08 +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */ +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +#define TIMER_INTCLR 0x0c +#define TIMER_RIS 0x10 +#define TIMER_MIS 0x14 +#define TIMER_BGLOAD 0x18 + +#endif diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h index 2114acb3d237..4f68c8a5a199 100644 --- a/include/asm-arm/ide.h +++ b/include/asm-arm/ide.h @@ -5,7 +5,7 @@ */ /* - * This file contains the i386 architecture specific IDE code. + * This file contains the ARM architecture specific IDE code. */ #ifndef __ASMARM_IDE_H diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 08a46302d265..cfa71a0dffb6 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -82,7 +82,7 @@ extern void __readwrite_bug(const char *fn); * only. Their primary purpose is to access PCI and ISA peripherals. * * Note that for a big endian machine, this implies that the following - * big endian mode connectivity is in place, as described by numerious + * big endian mode connectivity is in place, as described by numerous * ARM documents: * * PCI: D0-D7 D8-D15 D16-D23 D24-D31 @@ -275,6 +275,7 @@ extern void __iounmap(void __iomem *addr); /* * io{read,write}{8,16,32} macros */ +#ifndef ioread8 #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) #define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; }) #define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; }) @@ -293,6 +294,7 @@ extern void __iounmap(void __iomem *addr); extern void __iomem *ioport_map(unsigned long port, unsigned int nr); extern void ioport_unmap(void __iomem *addr); +#endif struct pci_dev; diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h index 5cf4fd659fd5..2cf279a44017 100644 --- a/include/asm-arm/mach/time.h +++ b/include/asm-arm/mach/time.h @@ -39,8 +39,31 @@ struct sys_timer { void (*suspend)(void); void (*resume)(void); unsigned long (*offset)(void); + +#ifdef CONFIG_NO_IDLE_HZ + struct dyn_tick_timer *dyn_tick; +#endif +}; + +#ifdef CONFIG_NO_IDLE_HZ + +#define DYN_TICK_SKIPPING (1 << 2) +#define DYN_TICK_ENABLED (1 << 1) +#define DYN_TICK_SUITABLE (1 << 0) + +struct dyn_tick_timer { + unsigned int state; /* Current state */ + int (*enable)(void); /* Enables dynamic tick */ + int (*disable)(void); /* Disables dynamic tick */ + void (*reprogram)(unsigned long); /* Reprograms the timer */ + int (*handler)(int, void *, struct pt_regs *); }; +void timer_dyn_reprogram(void); +#else +#define timer_dyn_reprogram() do { } while (0) +#endif + extern struct sys_timer *system_timer; extern void timer_tick(struct pt_regs *); diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index 40ffaefbeb1a..e300646fe650 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -42,6 +42,16 @@ static inline void pcibios_penalize_isa_irq(int irq) #define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) +#ifdef CONFIG_PCI +static inline void pci_dma_burst_advice(struct pci_dev *pdev, + enum pci_dma_burst_strategy *strat, + unsigned long *strategy_parameter) +{ + *strat = PCI_DMA_BURST_INFINITY; + *strategy_parameter = ~0UL; +} +#endif + #define HAVE_PCI_MMAP extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, enum pci_mmap_state mmap_state, int write_combine); diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h index 46e69ae395af..760f6e65af05 100644 --- a/include/asm-arm/signal.h +++ b/include/asm-arm/signal.h @@ -114,6 +114,7 @@ typedef unsigned long sigset_t; #define SIGSTKSZ 8192 #ifdef __KERNEL__ +#define SA_TIMER 0x40000000 #define SA_IRQNOMASK 0x08000000 #endif diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h index 39dd7008013c..cdf49f442fd2 100644 --- a/include/asm-arm/system.h +++ b/include/asm-arm/system.h @@ -145,34 +145,12 @@ extern unsigned int user_debug; #define set_wmb(var, value) do { var = value; wmb(); } while (0) #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); -#ifdef CONFIG_SMP /* - * Define our own context switch locking. This allows us to enable - * interrupts over the context switch, otherwise we end up with high - * interrupt latency. The real problem area is switch_mm() which may - * do a full cache flush. + * switch_mm() may do a full cache flush over the context switch, + * so enable interrupts over the context switch to avoid high + * latency. */ -#define prepare_arch_switch(rq,next) \ -do { \ - spin_lock(&(next)->switch_lock); \ - spin_unlock_irq(&(rq)->lock); \ -} while (0) - -#define finish_arch_switch(rq,prev) \ - spin_unlock(&(prev)->switch_lock) - -#define task_running(rq,p) \ - ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock)) -#else -/* - * Our UP-case is more simple, but we assume knowledge of how - * spin_unlock_irq() and friends are implemented. This avoids - * us needlessly decrementing and incrementing the preempt count. - */ -#define prepare_arch_switch(rq,next) local_irq_enable() -#define finish_arch_switch(rq,prev) spin_unlock(&(rq)->lock) -#define task_running(rq,p) ((rq)->curr == (p)) -#endif +#define __ARCH_WANT_INTERRUPTS_ON_CTXSW /* * switch_to(prev, next) should switch from task `prev' to `next' @@ -312,7 +290,6 @@ do { \ }) #ifdef CONFIG_SMP -#error SMP not supported #define smp_mb() mb() #define smp_rmb() rmb() @@ -326,6 +303,8 @@ do { \ #define smp_wmb() barrier() #define smp_read_barrier_depends() do { } while(0) +#endif /* CONFIG_SMP */ + #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) /* * On the StrongARM, "swp" is terminally broken since it bypasses the @@ -338,9 +317,16 @@ do { \ * * We choose (1) since its the "easiest" to achieve here and is not * dependent on the processor type. + * + * NOTE that this solution won't work on an SMP system, so explcitly + * forbid it here. */ +#ifdef CONFIG_SMP +#error SMP is not supported on SA1100/SA110 +#else #define swp_is_buggy #endif +#endif static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) { @@ -383,8 +369,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size return ret; } -#endif /* CONFIG_SMP */ - #endif /* __ASSEMBLY__ */ #define arch_align_stack(x) (x) diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 8a864b118569..9387a5e1ffe0 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -235,7 +235,7 @@ extern struct cpu_tlb_fns cpu_tlb; #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) -static inline void flush_tlb_all(void) +static inline void local_flush_tlb_all(void) { const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; @@ -253,7 +253,7 @@ static inline void flush_tlb_all(void) asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); } -static inline void flush_tlb_mm(struct mm_struct *mm) +static inline void local_flush_tlb_mm(struct mm_struct *mm) { const int zero = 0; const int asid = ASID(mm); @@ -282,7 +282,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) } static inline void -flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) +local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; @@ -313,7 +313,7 @@ flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); } -static inline void flush_tlb_kernel_page(unsigned long kaddr) +static inline void local_flush_tlb_kernel_page(unsigned long kaddr) { const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; @@ -384,8 +384,24 @@ static inline void clean_pmd_entry(pmd_t *pmd) /* * Convert calls to our calling convention. */ -#define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) -#define flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) +#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) +#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) + +#ifndef CONFIG_SMP +#define flush_tlb_all local_flush_tlb_all +#define flush_tlb_mm local_flush_tlb_mm +#define flush_tlb_page local_flush_tlb_page +#define flush_tlb_kernel_page local_flush_tlb_kernel_page +#define flush_tlb_range local_flush_tlb_range +#define flush_tlb_kernel_range local_flush_tlb_kernel_range +#else +extern void flush_tlb_all(void); +extern void flush_tlb_mm(struct mm_struct *mm); +extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr); +extern void flush_tlb_kernel_page(unsigned long kaddr); +extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); +extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); +#endif /* * if PG_dcache_dirty is set for the page, we need to ensure that any |
