diff options
Diffstat (limited to 'drivers')
26 files changed, 756 insertions, 104 deletions
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index b9e8cfc93c7e..0a52da439abf 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -112,6 +112,7 @@ config QCOM_EBI2 bool "Qualcomm External Bus Interface 2 (EBI2)" depends on HAS_IOMEM depends on ARCH_QCOM || COMPILE_TEST + default ARCH_QCOM help Say y here to enable support for the Qualcomm External Bus Interface 2, which can be used to connect things like NAND Flash, diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index c6aeedbdcbb0..8ad226c60374 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -560,3 +560,21 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) return ret ? : le32_to_cpu(out); } + +int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) +{ + struct { + __le32 state; + __le32 id; + } req; + __le32 scm_ret = 0; + int ret; + + req.state = cpu_to_le32(state); + req.id = cpu_to_le32(id); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE, + &req, sizeof(req), &scm_ret, sizeof(scm_ret)); + + return ret ? : le32_to_cpu(scm_ret); +} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 4a0f5ead4fb5..4b220abaf363 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -358,3 +358,19 @@ int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) return ret ? : res.a1; } + +int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id) +{ + struct qcom_scm_desc desc = {0}; + struct arm_smccc_res res; + int ret; + + desc.args[0] = state; + desc.args[1] = id; + desc.arginfo = QCOM_SCM_ARGS(2); + + ret = qcom_scm_call(dev, QCOM_SCM_SVC_BOOT, QCOM_SCM_SET_REMOTE_STATE, + &desc, &res); + + return ret ? : res.a1; +} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 893f953eaccf..d987bcc7489d 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -324,6 +324,12 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL(qcom_scm_is_available); +int qcom_scm_set_remote_state(u32 state, u32 id) +{ + return __qcom_scm_set_remote_state(__scm->dev, state, id); +} +EXPORT_SYMBOL(qcom_scm_set_remote_state); + static int qcom_scm_probe(struct platform_device *pdev) { struct qcom_scm *scm; @@ -387,7 +393,7 @@ static int qcom_scm_probe(struct platform_device *pdev) static const struct of_device_id qcom_scm_dt_match[] = { { .compatible = "qcom,scm-apq8064", - .data = (void *) SCM_HAS_CORE_CLK, + /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */ }, { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK, diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 3584b00fe7e6..6a0f15469344 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -15,6 +15,8 @@ #define QCOM_SCM_SVC_BOOT 0x1 #define QCOM_SCM_BOOT_ADDR 0x1 #define QCOM_SCM_BOOT_ADDR_MC 0x11 +#define QCOM_SCM_SET_REMOTE_STATE 0xa +extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id); #define QCOM_SCM_FLAG_HLOS 0x01 #define QCOM_SCM_FLAG_COLDBOOT_MC 0x02 diff --git a/drivers/memory/atmel-ebi.c b/drivers/memory/atmel-ebi.c index 047d6fcdcec2..4e83a8b92665 100644 --- a/drivers/memory/atmel-ebi.c +++ b/drivers/memory/atmel-ebi.c @@ -76,9 +76,11 @@ struct at91_ebi_caps { struct at91_ebi { struct clk *clk; - struct regmap *smc; struct regmap *matrix; - + struct { + struct regmap *regmap; + struct clk *clk; + } smc; struct regmap_field *ebi_csa; struct device *dev; @@ -93,7 +95,7 @@ static void at91sam9_ebi_get_config(struct at91_ebi_dev *ebid, struct at91_ebi_dev_config *conf) { struct at91sam9_smc_generic_fields *fields = &ebid->ebi->sam9; - unsigned int clk_rate = clk_get_rate(ebid->ebi->clk); + unsigned int clk_period = NSEC_PER_SEC / clk_get_rate(ebid->ebi->clk); struct at91sam9_ebi_dev_config *config = &conf->sam9; struct at91sam9_smc_timings *timings = &config->timings; unsigned int val; @@ -102,43 +104,43 @@ static void at91sam9_ebi_get_config(struct at91_ebi_dev *ebid, config->mode = val & ~AT91_SMC_TDF; val = (val & AT91_SMC_TDF) >> 16; - timings->tdf_ns = clk_rate * val; + timings->tdf_ns = clk_period * val; regmap_fields_read(fields->setup, conf->cs, &val); timings->ncs_rd_setup_ns = (val >> 24) & 0x1f; timings->ncs_rd_setup_ns += ((val >> 29) & 0x1) * 128; - timings->ncs_rd_setup_ns *= clk_rate; + timings->ncs_rd_setup_ns *= clk_period; timings->nrd_setup_ns = (val >> 16) & 0x1f; timings->nrd_setup_ns += ((val >> 21) & 0x1) * 128; - timings->nrd_setup_ns *= clk_rate; + timings->nrd_setup_ns *= clk_period; timings->ncs_wr_setup_ns = (val >> 8) & 0x1f; timings->ncs_wr_setup_ns += ((val >> 13) & 0x1) * 128; - timings->ncs_wr_setup_ns *= clk_rate; + timings->ncs_wr_setup_ns *= clk_period; timings->nwe_setup_ns = val & 0x1f; timings->nwe_setup_ns += ((val >> 5) & 0x1) * 128; - timings->nwe_setup_ns *= clk_rate; + timings->nwe_setup_ns *= clk_period; regmap_fields_read(fields->pulse, conf->cs, &val); timings->ncs_rd_pulse_ns = (val >> 24) & 0x3f; timings->ncs_rd_pulse_ns += ((val >> 30) & 0x1) * 256; - timings->ncs_rd_pulse_ns *= clk_rate; + timings->ncs_rd_pulse_ns *= clk_period; timings->nrd_pulse_ns = (val >> 16) & 0x3f; timings->nrd_pulse_ns += ((val >> 22) & 0x1) * 256; - timings->nrd_pulse_ns *= clk_rate; + timings->nrd_pulse_ns *= clk_period; timings->ncs_wr_pulse_ns = (val >> 8) & 0x3f; timings->ncs_wr_pulse_ns += ((val >> 14) & 0x1) * 256; - timings->ncs_wr_pulse_ns *= clk_rate; + timings->ncs_wr_pulse_ns *= clk_period; timings->nwe_pulse_ns = val & 0x3f; timings->nwe_pulse_ns += ((val >> 6) & 0x1) * 256; - timings->nwe_pulse_ns *= clk_rate; + timings->nwe_pulse_ns *= clk_period; regmap_fields_read(fields->cycle, conf->cs, &val); timings->nrd_cycle_ns = (val >> 16) & 0x7f; timings->nrd_cycle_ns += ((val >> 23) & 0x3) * 256; - timings->nrd_cycle_ns *= clk_rate; + timings->nrd_cycle_ns *= clk_period; timings->nwe_cycle_ns = val & 0x7f; timings->nwe_cycle_ns += ((val >> 7) & 0x3) * 256; - timings->nwe_cycle_ns *= clk_rate; + timings->nwe_cycle_ns *= clk_period; } static int at91_xlate_timing(struct device_node *np, const char *prop, @@ -334,6 +336,7 @@ static int at91sam9_ebi_apply_config(struct at91_ebi_dev *ebid, struct at91_ebi_dev_config *conf) { unsigned int clk_rate = clk_get_rate(ebid->ebi->clk); + unsigned int clk_period = NSEC_PER_SEC / clk_rate; struct at91sam9_ebi_dev_config *config = &conf->sam9; struct at91sam9_smc_timings *timings = &config->timings; struct at91sam9_smc_generic_fields *fields = &ebid->ebi->sam9; @@ -376,7 +379,7 @@ static int at91sam9_ebi_apply_config(struct at91_ebi_dev *ebid, val |= AT91SAM9_SMC_NWECYCLE(coded_val); regmap_fields_write(fields->cycle, conf->cs, val); - val = DIV_ROUND_UP(timings->tdf_ns, clk_rate); + val = DIV_ROUND_UP(timings->tdf_ns, clk_period); if (val > AT91_SMC_TDF_MAX) val = AT91_SMC_TDF_MAX; regmap_fields_write(fields->mode, conf->cs, @@ -394,22 +397,26 @@ static int at91sam9_ebi_init(struct at91_ebi *ebi) field.id_offset = AT91SAM9_SMC_GENERIC_BLK_SZ; field.reg = AT91SAM9_SMC_SETUP(AT91SAM9_SMC_GENERIC); - fields->setup = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->setup = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); if (IS_ERR(fields->setup)) return PTR_ERR(fields->setup); field.reg = AT91SAM9_SMC_PULSE(AT91SAM9_SMC_GENERIC); - fields->pulse = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->pulse = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); if (IS_ERR(fields->pulse)) return PTR_ERR(fields->pulse); field.reg = AT91SAM9_SMC_CYCLE(AT91SAM9_SMC_GENERIC); - fields->cycle = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->cycle = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); if (IS_ERR(fields->cycle)) return PTR_ERR(fields->cycle); field.reg = AT91SAM9_SMC_MODE(AT91SAM9_SMC_GENERIC); - fields->mode = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->mode = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); return PTR_ERR_OR_ZERO(fields->mode); } @@ -422,22 +429,26 @@ static int sama5d3_ebi_init(struct at91_ebi *ebi) field.id_offset = SAMA5_SMC_GENERIC_BLK_SZ; field.reg = AT91SAM9_SMC_SETUP(SAMA5_SMC_GENERIC); - fields->setup = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->setup = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); if (IS_ERR(fields->setup)) return PTR_ERR(fields->setup); field.reg = AT91SAM9_SMC_PULSE(SAMA5_SMC_GENERIC); - fields->pulse = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->pulse = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); if (IS_ERR(fields->pulse)) return PTR_ERR(fields->pulse); field.reg = AT91SAM9_SMC_CYCLE(SAMA5_SMC_GENERIC); - fields->cycle = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->cycle = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); if (IS_ERR(fields->cycle)) return PTR_ERR(fields->cycle); field.reg = SAMA5_SMC_MODE(SAMA5_SMC_GENERIC); - fields->mode = devm_regmap_field_alloc(ebi->dev, ebi->smc, field); + fields->mode = devm_regmap_field_alloc(ebi->dev, ebi->smc.regmap, + field); return PTR_ERR_OR_ZERO(fields->mode); } @@ -448,12 +459,31 @@ static int at91_ebi_dev_setup(struct at91_ebi *ebi, struct device_node *np, struct at91_ebi_dev_config conf = { }; struct device *dev = ebi->dev; struct at91_ebi_dev *ebid; - int ret, numcs = 0, i; + unsigned long cslines = 0; + int ret, numcs = 0, nentries, i; bool apply = false; + u32 cs; - numcs = of_property_count_elems_of_size(np, "reg", - reg_cells * sizeof(u32)); - if (numcs <= 0) { + nentries = of_property_count_elems_of_size(np, "reg", + reg_cells * sizeof(u32)); + for (i = 0; i < nentries; i++) { + ret = of_property_read_u32_index(np, "reg", i * reg_cells, + &cs); + if (ret) + return ret; + + if (cs >= AT91_MATRIX_EBI_NUM_CS || + !(ebi->caps->available_cs & BIT(cs))) { + dev_err(dev, "invalid reg property in %s\n", + np->full_name); + return -EINVAL; + } + + if (!test_and_set_bit(cs, &cslines)) + numcs++; + } + + if (!numcs) { dev_err(dev, "invalid reg property in %s\n", np->full_name); return -EINVAL; } @@ -472,21 +502,8 @@ static int at91_ebi_dev_setup(struct at91_ebi *ebi, struct device_node *np, else if (ret) apply = true; - for (i = 0; i < numcs; i++) { - u32 cs; - - ret = of_property_read_u32_index(np, "reg", i * reg_cells, - &cs); - if (ret) - return ret; - - if (cs > AT91_MATRIX_EBI_NUM_CS || - !(ebi->caps->available_cs & BIT(cs))) { - dev_err(dev, "invalid reg property in %s\n", - np->full_name); - return -EINVAL; - } - + i = 0; + for_each_set_bit(cs, &cslines, AT91_MATRIX_EBI_NUM_CS) { ebid->configs[i].cs = cs; if (apply) { @@ -502,9 +519,11 @@ static int at91_ebi_dev_setup(struct at91_ebi *ebi, struct device_node *np, * Attach the EBI device to the generic SMC logic if at least * one "atmel,smc-" property is present. */ - if (ebi->ebi_csa && ret) + if (ebi->ebi_csa && apply) regmap_field_update_bits(ebi->ebi_csa, BIT(cs), 0); + + i++; } list_add_tail(&ebid->node, &ebi->devs); @@ -668,7 +687,7 @@ static int at91_ebi_dev_disable(struct at91_ebi *ebi, struct device_node *np) static int at91_ebi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *child, *np = dev->of_node; + struct device_node *child, *np = dev->of_node, *smc_np; const struct of_device_id *match; struct at91_ebi *ebi; int ret, reg_cells; @@ -693,9 +712,22 @@ static int at91_ebi_probe(struct platform_device *pdev) ebi->clk = clk; - ebi->smc = syscon_regmap_lookup_by_phandle(np, "atmel,smc"); - if (IS_ERR(ebi->smc)) - return PTR_ERR(ebi->smc); + smc_np = of_parse_phandle(dev->of_node, "atmel,smc", 0); + + ebi->smc.regmap = syscon_node_to_regmap(smc_np); + if (IS_ERR(ebi->smc.regmap)) + return PTR_ERR(ebi->smc.regmap); + + ebi->smc.clk = of_clk_get(smc_np, 0); + if (IS_ERR(ebi->smc.clk)) { + if (PTR_ERR(ebi->smc.clk) != -ENOENT) + return PTR_ERR(ebi->smc.clk); + + ebi->smc.clk = NULL; + } + ret = clk_prepare_enable(ebi->smc.clk); + if (ret) + return ret; /* * The sama5d3 does not provide an EBICSA register and thus does need diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 06cc781ebac1..392dc8dd481f 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1115,11 +1115,10 @@ static int tegra_emc_probe(struct platform_device *pdev) } mc = of_find_device_by_node(np); + of_node_put(np); if (!mc) return -ENOENT; - of_node_put(np); - emc->mc = platform_get_drvdata(mc); if (!emc->mc) return -EPROBE_DEFER; @@ -1135,9 +1134,7 @@ static int tegra_emc_probe(struct platform_device *pdev) } err = tegra_emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) return err; diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index f31bceb69c0d..f09023f7ab11 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -11,5 +11,6 @@ source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/ux500/Kconfig" source "drivers/soc/versatile/Kconfig" +source "drivers/soc/zte/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 50c23d0bd457..05eae52a30b4 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_PLAT_VERSATILE) += versatile/ +obj-$(CONFIG_ARCH_ZX) += zte/ diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig index 7140ff825598..20da55d9cbb1 100644 --- a/drivers/soc/rockchip/Kconfig +++ b/drivers/soc/rockchip/Kconfig @@ -3,6 +3,16 @@ if ARCH_ROCKCHIP || COMPILE_TEST # # Rockchip Soc drivers # + +config ROCKCHIP_GRF + bool + default y + help + The General Register Files are a central component providing + special additional settings registers for a lot of soc-components. + In a lot of cases there also need to be default settings initialized + to make some of them conform to expectations of the kernel. + config ROCKCHIP_PM_DOMAINS bool "Rockchip generic power domain" depends on PM diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile index 3d73d0672d22..c851fa0056d0 100644 --- a/drivers/soc/rockchip/Makefile +++ b/drivers/soc/rockchip/Makefile @@ -1,4 +1,5 @@ # # Rockchip Soc drivers # +obj-$(CONFIG_ROCKCHIP_GRF) += grf.o obj-$(CONFIG_ROCKCHIP_PM_DOMAINS) += pm_domains.o diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c new file mode 100644 index 000000000000..d61db34ad6dd --- /dev/null +++ b/drivers/soc/rockchip/grf.c @@ -0,0 +1,134 @@ +/* + * Rockchip Generic Register Files setup + * + * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/mfd/syscon.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define HIWORD_UPDATE(val, mask, shift) \ + ((val) << (shift) | (mask) << ((shift) + 16)) + +struct rockchip_grf_value { + const char *desc; + u32 reg; + u32 val; +}; + +struct rockchip_grf_info { + const struct rockchip_grf_value *values; + int num_values; +}; + +#define RK3036_GRF_SOC_CON0 0x140 + +static const struct rockchip_grf_value rk3036_defaults[] __initconst = { + /* + * Disable auto jtag/sdmmc switching that causes issues with the + * clock-framework and the mmc controllers making them unreliable. + */ + { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) }, +}; + +static const struct rockchip_grf_info rk3036_grf __initconst = { + .values = rk3036_defaults, + .num_values = ARRAY_SIZE(rk3036_defaults), +}; + +#define RK3288_GRF_SOC_CON0 0x244 + +static const struct rockchip_grf_value rk3288_defaults[] __initconst = { + { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) }, +}; + +static const struct rockchip_grf_info rk3288_grf __initconst = { + .values = rk3288_defaults, + .num_values = ARRAY_SIZE(rk3288_defaults), +}; + +#define RK3368_GRF_SOC_CON15 0x43c + +static const struct rockchip_grf_value rk3368_defaults[] __initconst = { + { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) }, +}; + +static const struct rockchip_grf_info rk3368_grf __initconst = { + .values = rk3368_defaults, + .num_values = ARRAY_SIZE(rk3368_defaults), +}; + +#define RK3399_GRF_SOC_CON7 0xe21c + +static const struct rockchip_grf_value rk3399_defaults[] __initconst = { + { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) }, +}; + +static const struct rockchip_grf_info rk3399_grf __initconst = { + .values = rk3399_defaults, + .num_values = ARRAY_SIZE(rk3399_defaults), +}; + +static const struct of_device_id rockchip_grf_dt_match[] __initconst = { + { + .compatible = "rockchip,rk3036-grf", + .data = (void *)&rk3036_grf, + }, { + .compatible = "rockchip,rk3288-grf", + .data = (void *)&rk3288_grf, + }, { + .compatible = "rockchip,rk3368-grf", + .data = (void *)&rk3368_grf, + }, { + .compatible = "rockchip,rk3399-grf", + .data = (void *)&rk3399_grf, + }, + { /* sentinel */ }, +}; + +static int __init rockchip_grf_init(void) +{ + const struct rockchip_grf_info *grf_info; + const struct of_device_id *match; + struct device_node *np; + struct regmap *grf; + int ret, i; + + np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match, + &match); + if (!np) + return -ENODEV; + if (!match || !match->data) { + pr_err("%s: missing grf data\n", __func__); + return -EINVAL; + } + + grf_info = match->data; + + grf = syscon_node_to_regmap(np); + if (IS_ERR(grf)) { + pr_err("%s: could not get grf syscon\n", __func__); + return PTR_ERR(grf); + } + + for (i = 0; i < grf_info->num_values; i++) { + const struct rockchip_grf_value *val = &grf_info->values[i]; + + pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__, + val->desc, val->reg, val->val); + ret = regmap_write(grf, val->reg, val->val); + if (ret < 0) + pr_err("%s: write to %#6x failed with %d\n", + __func__, val->reg, ret); + } + + return 0; +} +postcore_initcall(rockchip_grf_init); diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 1c78c42416c6..796c46a6cbe7 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -19,6 +19,7 @@ #include <linux/regmap.h> #include <linux/mfd/syscon.h> #include <dt-bindings/power/rk3288-power.h> +#include <dt-bindings/power/rk3328-power.h> #include <dt-bindings/power/rk3368-power.h> #include <dt-bindings/power/rk3399-power.h> @@ -29,6 +30,8 @@ struct rockchip_domain_info { int idle_mask; int ack_mask; bool active_wakeup; + int pwr_w_mask; + int req_w_mask; }; struct rockchip_pmu_info { @@ -87,9 +90,24 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } +#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +{ \ + .pwr_w_mask = (pwr >= 0) ? BIT(pwr + 16) : 0, \ + .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \ + .status_mask = (status >= 0) ? BIT(status) : 0, \ + .req_w_mask = (req >= 0) ? BIT(req + 16) : 0, \ + .req_mask = (req >= 0) ? BIT(req) : 0, \ + .idle_mask = (idle >= 0) ? BIT(idle) : 0, \ + .ack_mask = (ack >= 0) ? BIT(ack) : 0, \ + .active_wakeup = wakeup, \ +} + #define DOMAIN_RK3288(pwr, status, req, wakeup) \ DOMAIN(pwr, status, req, req, (req) + 16, wakeup) +#define DOMAIN_RK3328(pwr, status, req, wakeup) \ + DOMAIN_M(pwr, pwr, req, (req) + 10, req, wakeup) + #define DOMAIN_RK3368(pwr, status, req, wakeup) \ DOMAIN(pwr, status, req, (req) + 16, req, wakeup) @@ -127,9 +145,13 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, if (pd_info->req_mask == 0) return 0; - - regmap_update_bits(pmu->regmap, pmu->info->req_offset, - pd_info->req_mask, idle ? -1U : 0); + else if (pd_info->req_w_mask) + regmap_write(pmu->regmap, pmu->info->req_offset, + idle ? (pd_info->req_mask | pd_info->req_w_mask) : + pd_info->req_w_mask); + else + regmap_update_bits(pmu->regmap, pmu->info->req_offset, + pd_info->req_mask, idle ? -1U : 0); dsb(sy); @@ -230,9 +252,13 @@ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, if (pd->info->pwr_mask == 0) return; - - regmap_update_bits(pmu->regmap, pmu->info->pwr_offset, - pd->info->pwr_mask, on ? 0 : -1U); + else if (pd->info->pwr_w_mask) + regmap_write(pmu->regmap, pmu->info->pwr_offset, + on ? pd->info->pwr_mask : + (pd->info->pwr_mask | pd->info->pwr_w_mask)); + else + regmap_update_bits(pmu->regmap, pmu->info->pwr_offset, + pd->info->pwr_mask, on ? 0 : -1U); dsb(sy); @@ -692,6 +718,18 @@ static const struct rockchip_domain_info rk3288_pm_domains[] = { [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2, false), }; +static const struct rockchip_domain_info rk3328_pm_domains[] = { + [RK3328_PD_CORE] = DOMAIN_RK3328(-1, 0, 0, false), + [RK3328_PD_GPU] = DOMAIN_RK3328(-1, 1, 1, false), + [RK3328_PD_BUS] = DOMAIN_RK3328(-1, 2, 2, true), + [RK3328_PD_MSCH] = DOMAIN_RK3328(-1, 3, 3, true), + [RK3328_PD_PERI] = DOMAIN_RK3328(-1, 4, 4, true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328(-1, 5, 5, false), + [RK3328_PD_HEVC] = DOMAIN_RK3328(-1, 6, 6, false), + [RK3328_PD_VIO] = DOMAIN_RK3328(-1, 8, 8, false), + [RK3328_PD_VPU] = DOMAIN_RK3328(-1, 9, 9, false), +}; + static const struct rockchip_domain_info rk3368_pm_domains[] = { [RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6, true), [RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8, false), @@ -747,6 +785,15 @@ static const struct rockchip_pmu_info rk3288_pmu = { .domain_info = rk3288_pm_domains, }; +static const struct rockchip_pmu_info rk3328_pmu = { + .req_offset = 0x414, + .idle_offset = 0x484, + .ack_offset = 0x484, + + .num_domains = ARRAY_SIZE(rk3328_pm_domains), + .domain_info = rk3328_pm_domains, +}; + static const struct rockchip_pmu_info rk3368_pmu = { .pwr_offset = 0x0c, .status_offset = 0x10, @@ -783,6 +830,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .data = (void *)&rk3288_pmu, }, { + .compatible = "rockchip,rk3328-power-controller", + .data = (void *)&rk3328_pmu, + }, + { .compatible = "rockchip,rk3368-power-controller", .data = (void *)&rk3368_pmu, }, diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 0acdfd82e751..56d9244ff981 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -11,6 +11,8 @@ #include <linux/of.h> #include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/mfd/syscon.h> #include <linux/platform_device.h> #include <linux/delay.h> @@ -42,7 +44,7 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) unsigned int i; const struct exynos_pmu_data *pmu_data; - if (!pmu_context) + if (!pmu_context || !pmu_context->pmu_data) return; pmu_data = pmu_context->pmu_data; @@ -88,13 +90,24 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos5420-pmu", .data = &exynos5420_pmu_data, + }, { + .compatible = "samsung,exynos5433-pmu", }, { /*sentinel*/ }, }; +struct regmap *exynos_get_pmu_regmap(void) +{ + struct device_node *np = of_find_matching_node(NULL, + exynos_pmu_of_device_ids); + if (np) + return syscon_node_to_regmap(np); + return ERR_PTR(-ENODEV); +} +EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap); + static int exynos_pmu_probe(struct platform_device *pdev) { - const struct of_device_id *match; struct device *dev = &pdev->dev; struct resource *res; @@ -106,17 +119,12 @@ static int exynos_pmu_probe(struct platform_device *pdev) pmu_context = devm_kzalloc(&pdev->dev, sizeof(struct exynos_pmu_context), GFP_KERNEL); - if (!pmu_context) { - dev_err(dev, "Cannot allocate memory.\n"); + if (!pmu_context) return -ENOMEM; - } pmu_context->dev = dev; + pmu_context->pmu_data = of_device_get_match_data(dev); - match = of_match_node(exynos_pmu_of_device_ids, dev->of_node); - - pmu_context->pmu_data = match->data; - - if (pmu_context->pmu_data->pmu_init) + if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init) pmu_context->pmu_data->pmu_init(); platform_set_drvdata(pdev, pmu_context); diff --git a/drivers/soc/samsung/exynos5250-pmu.c b/drivers/soc/samsung/exynos5250-pmu.c index 3fac42561964..8d94f0819f32 100644 --- a/drivers/soc/samsung/exynos5250-pmu.c +++ b/drivers/soc/samsung/exynos5250-pmu.c @@ -29,7 +29,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = { { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, - { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } }, + { EXYNOS_L2_OPTION(0), { 0x10, 0x10, 0x0 } }, { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, diff --git a/drivers/soc/samsung/exynos5420-pmu.c b/drivers/soc/samsung/exynos5420-pmu.c index 3f2c64180ef8..0a89fa79c678 100644 --- a/drivers/soc/samsung/exynos5420-pmu.c +++ b/drivers/soc/samsung/exynos5420-pmu.c @@ -230,11 +230,11 @@ static void exynos5420_pmu_init(void) pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); value = pmu_raw_readl(EXYNOS_L2_OPTION(0)); - value &= ~EXYNOS5_USE_RETENTION; + value &= ~EXYNOS_L2_USE_RETENTION; pmu_raw_writel(value, EXYNOS_L2_OPTION(0)); value = pmu_raw_readl(EXYNOS_L2_OPTION(1)); - value &= ~EXYNOS5_USE_RETENTION; + value &= ~EXYNOS_L2_USE_RETENTION; pmu_raw_writel(value, EXYNOS_L2_OPTION(1)); /* diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index 7112004b8032..15bad1543409 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -128,10 +128,17 @@ static const struct exynos_pm_domain_config exynos4210_cfg __initconst = { .local_pwr_cfg = 0x7, }; +static const struct exynos_pm_domain_config exynos5433_cfg __initconst = { + .local_pwr_cfg = 0xf, +}; + static const struct of_device_id exynos_pm_domain_of_match[] __initconst = { { .compatible = "samsung,exynos4210-pd", .data = &exynos4210_cfg, + }, { + .compatible = "samsung,exynos5433-pd", + .data = &exynos5433_cfg, }, { }, }; diff --git a/drivers/soc/ti/knav_dma.c b/drivers/soc/ti/knav_dma.c index 1a7b5caa127b..ecebe2eecc3a 100644 --- a/drivers/soc/ti/knav_dma.c +++ b/drivers/soc/ti/knav_dma.c @@ -395,7 +395,7 @@ static int of_channel_match_helper(struct device_node *np, const char *name, if (of_parse_phandle_with_fixed_args(np, "ti,navigator-dmas", 1, index, &args)) { - dev_err(kdev->dev, "Missing the pahndle args name %s\n", name); + dev_err(kdev->dev, "Missing the phandle args name %s\n", name); return -ENODEV; } @@ -436,7 +436,7 @@ void *knav_dma_open_channel(struct device *dev, const char *name, } dev_dbg(kdev->dev, "initializing %s channel %d from DMA %s\n", - config->direction == DMA_MEM_TO_DEV ? "transmit" : + config->direction == DMA_MEM_TO_DEV ? "transmit" : config->direction == DMA_DEV_TO_MEM ? "receive" : "unknown", chan_num, instance); diff --git a/drivers/soc/ti/knav_qmss_acc.c b/drivers/soc/ti/knav_qmss_acc.c index 0612ebae0a09..3d7225f4e77f 100644 --- a/drivers/soc/ti/knav_qmss_acc.c +++ b/drivers/soc/ti/knav_qmss_acc.c @@ -16,21 +16,12 @@ * General Public License for more details. */ -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/device.h> +#include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include <linux/soc/ti/knav_qmss.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/of.h> -#include <linux/of_device.h> +#include <linux/module.h> #include <linux/of_address.h> -#include <linux/firmware.h> +#include <linux/soc/ti/knav_qmss.h> #include "knav_qmss.h" diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index eacad57f2977..279e7c5551dd 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -16,26 +16,17 @@ * General Public License for more details. */ -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/device.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/bitops.h> -#include <linux/slab.h> -#include <linux/spinlock.h> -#include <linux/platform_device.h> +#include <linux/debugfs.h> #include <linux/dma-mapping.h> -#include <linux/of.h> -#include <linux/of_irq.h> -#include <linux/of_device.h> +#include <linux/firmware.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> #include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> #include <linux/pm_runtime.h> -#include <linux/firmware.h> -#include <linux/debugfs.h> -#include <linux/seq_file.h> -#include <linux/string.h> +#include <linux/slab.h> #include <linux/soc/ti/knav_qmss.h> #include "knav_qmss.h" diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 8823cc81ae45..8bfa44b08e03 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -370,8 +370,6 @@ static void wkup_m3_rproc_boot_thread(struct wkup_m3_ipc *m3_ipc) struct device *dev = m3_ipc->dev; int ret; - wait_for_completion(&m3_ipc->rproc->firmware_loading_complete); - init_completion(&m3_ipc->sync_complete); ret = rproc_boot(m3_ipc->rproc); diff --git a/drivers/soc/zte/Kconfig b/drivers/soc/zte/Kconfig new file mode 100644 index 000000000000..20bde38ce2f9 --- /dev/null +++ b/drivers/soc/zte/Kconfig @@ -0,0 +1,13 @@ +# +# ZTE SoC drivers +# +menuconfig SOC_ZTE + bool "ZTE SoC driver support" + +if SOC_ZTE + +config ZX2967_PM_DOMAINS + bool "ZX2967 PM domains" + depends on PM_GENERIC_DOMAINS + +endif diff --git a/drivers/soc/zte/Makefile b/drivers/soc/zte/Makefile new file mode 100644 index 000000000000..96b7cd4c9629 --- /dev/null +++ b/drivers/soc/zte/Makefile @@ -0,0 +1,5 @@ +# +# ZTE SOC drivers +# +obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx2967_pm_domains.o +obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx296718_pm_domains.o diff --git a/drivers/soc/zte/zx296718_pm_domains.c b/drivers/soc/zte/zx296718_pm_domains.c new file mode 100644 index 000000000000..5ed924fee855 --- /dev/null +++ b/drivers/soc/zte/zx296718_pm_domains.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie <baoyou.xie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <dt-bindings/soc/zte,pm_domains.h> +#include "zx2967_pm_domains.h" + +static u16 zx296718_offsets[REG_ARRAY_SIZE] = { + [REG_CLKEN] = 0x18, + [REG_ISOEN] = 0x1c, + [REG_RSTEN] = 0x20, + [REG_PWREN] = 0x24, + [REG_ACK_SYNC] = 0x28, +}; + +enum { + PCU_DM_VOU = 0, + PCU_DM_SAPPU, + PCU_DM_VDE, + PCU_DM_VCE, + PCU_DM_HDE, + PCU_DM_VIU, + PCU_DM_USB20, + PCU_DM_USB21, + PCU_DM_USB30, + PCU_DM_HSIC, + PCU_DM_GMAC, + PCU_DM_TS, +}; + +static struct zx2967_pm_domain vou_domain = { + .dm = { + .name = "vou_domain", + }, + .bit = PCU_DM_VOU, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain sappu_domain = { + .dm = { + .name = "sappu_domain", + }, + .bit = PCU_DM_SAPPU, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain vde_domain = { + .dm = { + .name = "vde_domain", + }, + .bit = PCU_DM_VDE, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain vce_domain = { + .dm = { + .name = "vce_domain", + }, + .bit = PCU_DM_VCE, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain hde_domain = { + .dm = { + .name = "hde_domain", + }, + .bit = PCU_DM_HDE, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain viu_domain = { + .dm = { + .name = "viu_domain", + }, + .bit = PCU_DM_VIU, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain usb20_domain = { + .dm = { + .name = "usb20_domain", + }, + .bit = PCU_DM_USB20, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain usb21_domain = { + .dm = { + .name = "usb21_domain", + }, + .bit = PCU_DM_USB21, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain usb30_domain = { + .dm = { + .name = "usb30_domain", + }, + .bit = PCU_DM_USB30, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain hsic_domain = { + .dm = { + .name = "hsic_domain", + }, + .bit = PCU_DM_HSIC, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain gmac_domain = { + .dm = { + .name = "gmac_domain", + }, + .bit = PCU_DM_GMAC, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct zx2967_pm_domain ts_domain = { + .dm = { + .name = "ts_domain", + }, + .bit = PCU_DM_TS, + .polarity = PWREN, + .reg_offset = zx296718_offsets, +}; + +static struct generic_pm_domain *zx296718_pm_domains[] = { + [DM_ZX296718_VOU] = &vou_domain.dm, + [DM_ZX296718_SAPPU] = &sappu_domain.dm, + [DM_ZX296718_VDE] = &vde_domain.dm, + [DM_ZX296718_VCE] = &vce_domain.dm, + [DM_ZX296718_HDE] = &hde_domain.dm, + [DM_ZX296718_VIU] = &viu_domain.dm, + [DM_ZX296718_USB20] = &usb20_domain.dm, + [DM_ZX296718_USB21] = &usb21_domain.dm, + [DM_ZX296718_USB30] = &usb30_domain.dm, + [DM_ZX296718_HSIC] = &hsic_domain.dm, + [DM_ZX296718_GMAC] = &gmac_domain.dm, + [DM_ZX296718_TS] = &ts_domain.dm, +}; + +static int zx296718_pd_probe(struct platform_device *pdev) +{ + return zx2967_pd_probe(pdev, + zx296718_pm_domains, + ARRAY_SIZE(zx296718_pm_domains)); +} + +static const struct of_device_id zx296718_pm_domain_matches[] = { + { .compatible = "zte,zx296718-pcu", }, + { }, +}; + +static struct platform_driver zx296718_pd_driver = { + .driver = { + .name = "zx296718-powerdomain", + .owner = THIS_MODULE, + .of_match_table = zx296718_pm_domain_matches, + }, + .probe = zx296718_pd_probe, +}; + +static int __init zx296718_pd_init(void) +{ + return platform_driver_register(&zx296718_pd_driver); +} +subsys_initcall(zx296718_pd_init); diff --git a/drivers/soc/zte/zx2967_pm_domains.c b/drivers/soc/zte/zx2967_pm_domains.c new file mode 100644 index 000000000000..61c8d84bf315 --- /dev/null +++ b/drivers/soc/zte/zx2967_pm_domains.c @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie <baoyou.xie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/of.h> + +#include "zx2967_pm_domains.h" + +#define PCU_DM_CLKEN(zpd) ((zpd)->reg_offset[REG_CLKEN]) +#define PCU_DM_ISOEN(zpd) ((zpd)->reg_offset[REG_ISOEN]) +#define PCU_DM_RSTEN(zpd) ((zpd)->reg_offset[REG_RSTEN]) +#define PCU_DM_PWREN(zpd) ((zpd)->reg_offset[REG_PWREN]) +#define PCU_DM_ACK_SYNC(zpd) ((zpd)->reg_offset[REG_ACK_SYNC]) + +static void __iomem *pcubase; + +static int zx2967_power_on(struct generic_pm_domain *domain) +{ + struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain; + unsigned long loop = 1000; + u32 val; + + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd)); + if (zpd->polarity == PWREN) + val |= BIT(zpd->bit); + else + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd)); + + do { + udelay(1); + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd)) + & BIT(zpd->bit); + } while (--loop && !val); + + if (!loop) { + pr_err("Error: %s %s fail\n", __func__, domain->name); + return -EIO; + } + + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd)); + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd)); + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd)); + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd)); + udelay(5); + + pr_debug("poweron %s\n", domain->name); + + return 0; +} + +static int zx2967_power_off(struct generic_pm_domain *domain) +{ + struct zx2967_pm_domain *zpd = (struct zx2967_pm_domain *)domain; + unsigned long loop = 1000; + u32 val; + + val = readl_relaxed(pcubase + PCU_DM_CLKEN(zpd)); + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_CLKEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_ISOEN(zpd)); + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_ISOEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_RSTEN(zpd)); + val &= ~BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_RSTEN(zpd)); + udelay(5); + + val = readl_relaxed(pcubase + PCU_DM_PWREN(zpd)); + if (zpd->polarity == PWREN) + val &= ~BIT(zpd->bit); + else + val |= BIT(zpd->bit); + writel_relaxed(val, pcubase + PCU_DM_PWREN(zpd)); + + do { + udelay(1); + val = readl_relaxed(pcubase + PCU_DM_ACK_SYNC(zpd)) + & BIT(zpd->bit); + } while (--loop && val); + + if (!loop) { + pr_err("Error: %s %s fail\n", __func__, domain->name); + return -EIO; + } + + pr_debug("poweroff %s\n", domain->name); + + return 0; +} + +int zx2967_pd_probe(struct platform_device *pdev, + struct generic_pm_domain **zx_pm_domains, + int domain_num) +{ + struct genpd_onecell_data *genpd_data; + struct resource *res; + int i; + + genpd_data = devm_kzalloc(&pdev->dev, sizeof(*genpd_data), GFP_KERNEL); + if (!genpd_data) + return -ENOMEM; + + genpd_data->domains = zx_pm_domains; + genpd_data->num_domains = domain_num; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pcubase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pcubase)) { + dev_err(&pdev->dev, "ioremap fail.\n"); + return PTR_ERR(pcubase); + } + + for (i = 0; i < domain_num; ++i) { + zx_pm_domains[i]->power_on = zx2967_power_on; + zx_pm_domains[i]->power_off = zx2967_power_off; + + pm_genpd_init(zx_pm_domains[i], NULL, false); + } + + of_genpd_add_provider_onecell(pdev->dev.of_node, genpd_data); + dev_info(&pdev->dev, "powerdomain init ok\n"); + return 0; +} diff --git a/drivers/soc/zte/zx2967_pm_domains.h b/drivers/soc/zte/zx2967_pm_domains.h new file mode 100644 index 000000000000..cb46595a7ff3 --- /dev/null +++ b/drivers/soc/zte/zx2967_pm_domains.h @@ -0,0 +1,44 @@ +/* + * Header for ZTE's Power Domain Driver support + * + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie <baoyou.xie@linaro.org> + * License terms: GNU General Public License (GPL) version 2 + */ + +#ifndef __ZTE_ZX2967_PM_DOMAIN_H +#define __ZTE_ZX2967_PM_DOMAIN_H + +#include <linux/platform_device.h> +#include <linux/pm_domain.h> + +enum { + REG_CLKEN, + REG_ISOEN, + REG_RSTEN, + REG_PWREN, + REG_PWRDN, + REG_ACK_SYNC, + + /* The size of the array - must be last */ + REG_ARRAY_SIZE, +}; + +enum zx2967_power_polarity { + PWREN, + PWRDN, +}; + +struct zx2967_pm_domain { + struct generic_pm_domain dm; + const u16 bit; + const enum zx2967_power_polarity polarity; + const u16 *reg_offset; +}; + +int zx2967_pd_probe(struct platform_device *pdev, + struct generic_pm_domain **zx_pm_domains, + int domain_num); + +#endif /* __ZTE_ZX2967_PM_DOMAIN_H */ |
