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-rw-r--r--drivers/media/video/cx18/cx18-driver.c1
-rw-r--r--drivers/media/video/cx18/cx18-driver.h2
-rw-r--r--drivers/media/video/cx18/cx18-irq.c54
-rw-r--r--drivers/media/video/cx18/cx18-scb.h40
4 files changed, 49 insertions, 48 deletions
diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c
index 6a840f2d81a0..2befa3819cdb 100644
--- a/drivers/media/video/cx18/cx18-driver.c
+++ b/drivers/media/video/cx18/cx18-driver.c
@@ -448,7 +448,6 @@ static int __devinit cx18_init_struct1(struct cx18 *cx)
mutex_init(&cx->gpio_lock);
spin_lock_init(&cx->lock);
- spin_lock_init(&cx->dma_reg_lock);
/* start counting open_id at 1 */
cx->open_id = 1;
diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h
index a4b1708fafe7..e721c01d2178 100644
--- a/drivers/media/video/cx18/cx18-driver.h
+++ b/drivers/media/video/cx18/cx18-driver.h
@@ -402,8 +402,6 @@ struct cx18 {
spinlock_t lock; /* lock access to this struct */
int search_pack_header;
- spinlock_t dma_reg_lock; /* lock access to DMA engine registers */
-
int open_id; /* incremented each time an open occurs, used as
unique ID. Starts at 1, so 0 can be used as
uninitialized value in the stream->id. */
diff --git a/drivers/media/video/cx18/cx18-irq.c b/drivers/media/video/cx18/cx18-irq.c
index a366259bbb7b..c306e142c1c3 100644
--- a/drivers/media/video/cx18/cx18-irq.c
+++ b/drivers/media/video/cx18/cx18-irq.c
@@ -30,8 +30,6 @@
#include "cx18-vbi.h"
#include "cx18-scb.h"
-#define DMA_MAGIC_COOKIE 0x000001fe
-
static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
{
u32 handle = mb->args[0];
@@ -109,7 +107,7 @@ static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb)
CX18_INFO("FW version: %s\n", p - 1);
}
-static void hpu_cmd(struct cx18 *cx, u32 sw1)
+static void epu_cmd(struct cx18 *cx, u32 sw1)
{
struct cx18_mailbox mb;
@@ -125,12 +123,31 @@ static void hpu_cmd(struct cx18 *cx, u32 sw1)
epu_debug(cx, &mb);
break;
default:
- CX18_WARN("Unexpected mailbox command %08x\n", mb.cmd);
+ CX18_WARN("Unknown CPU_TO_EPU mailbox command %#08x\n",
+ mb.cmd);
break;
}
}
- if (sw1 & (IRQ_APU_TO_EPU | IRQ_HPU_TO_EPU))
- CX18_WARN("Unexpected interrupt %08x\n", sw1);
+
+ if (sw1 & IRQ_APU_TO_EPU) {
+ cx18_memcpy_fromio(cx, &mb, &cx->scb->apu2epu_mb, sizeof(mb));
+ CX18_WARN("Unknown APU_TO_EPU mailbox command %#08x\n", mb.cmd);
+ }
+
+ if (sw1 & IRQ_HPU_TO_EPU) {
+ cx18_memcpy_fromio(cx, &mb, &cx->scb->hpu2epu_mb, sizeof(mb));
+ CX18_WARN("Unknown HPU_TO_EPU mailbox command %#08x\n", mb.cmd);
+ }
+}
+
+static void xpu_ack(struct cx18 *cx, u32 sw2)
+{
+ if (sw2 & IRQ_CPU_TO_EPU_ACK)
+ wake_up(&cx->mb_cpu_waitq);
+ if (sw2 & IRQ_APU_TO_EPU_ACK)
+ wake_up(&cx->mb_apu_waitq);
+ if (sw2 & IRQ_HPU_TO_EPU_ACK)
+ wake_up(&cx->mb_hpu_waitq);
}
irqreturn_t cx18_irq_handler(int irq, void *dev_id)
@@ -140,11 +157,9 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
u32 sw2, sw2_mask;
u32 hw2, hw2_mask;
- spin_lock(&cx->dma_reg_lock);
-
- sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
+ sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
- sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK;
+ sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI);
hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask;
@@ -160,26 +175,15 @@ irqreturn_t cx18_irq_handler(int irq, void *dev_id)
CX18_DEBUG_HI_IRQ("SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
/* To do: interrupt-based I2C handling
- if (hw2 & 0x00c00000) {
+ if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
}
*/
- if (sw2) {
- if (sw2 & (cx18_readl(cx, &cx->scb->cpu2hpu_irq_ack) |
- cx18_readl(cx, &cx->scb->cpu2epu_irq_ack)))
- wake_up(&cx->mb_cpu_waitq);
- if (sw2 & (cx18_readl(cx, &cx->scb->apu2hpu_irq_ack) |
- cx18_readl(cx, &cx->scb->apu2epu_irq_ack)))
- wake_up(&cx->mb_apu_waitq);
- if (sw2 & cx18_readl(cx, &cx->scb->epu2hpu_irq_ack))
- wake_up(&cx->mb_epu_waitq);
- if (sw2 & cx18_readl(cx, &cx->scb->hpu2epu_irq_ack))
- wake_up(&cx->mb_hpu_waitq);
- }
+ if (sw2)
+ xpu_ack(cx, sw2);
if (sw1)
- hpu_cmd(cx, sw1);
- spin_unlock(&cx->dma_reg_lock);
+ epu_cmd(cx, sw1);
return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
}
diff --git a/drivers/media/video/cx18/cx18-scb.h b/drivers/media/video/cx18/cx18-scb.h
index 86b4cb15d163..594713bbed68 100644
--- a/drivers/media/video/cx18/cx18-scb.h
+++ b/drivers/media/video/cx18/cx18-scb.h
@@ -128,22 +128,22 @@ struct cx18_scb {
u32 apu2cpu_irq;
/* Value to write to register SW2 register set (0xC7003140) after the
command is cleared */
- u32 apu2cpu_irq_ack;
+ u32 cpu2apu_irq_ack;
u32 reserved2[13];
u32 hpu2cpu_mb_offset;
u32 hpu2cpu_irq;
- u32 hpu2cpu_irq_ack;
+ u32 cpu2hpu_irq_ack;
u32 reserved3[13];
u32 ppu2cpu_mb_offset;
u32 ppu2cpu_irq;
- u32 ppu2cpu_irq_ack;
+ u32 cpu2ppu_irq_ack;
u32 reserved4[13];
u32 epu2cpu_mb_offset;
u32 epu2cpu_irq;
- u32 epu2cpu_irq_ack;
+ u32 cpu2epu_irq_ack;
u32 reserved5[13];
u32 reserved6[8];
@@ -153,22 +153,22 @@ struct cx18_scb {
u32 reserved11[7];
u32 cpu2apu_mb_offset;
u32 cpu2apu_irq;
- u32 cpu2apu_irq_ack;
+ u32 apu2cpu_irq_ack;
u32 reserved12[13];
u32 hpu2apu_mb_offset;
u32 hpu2apu_irq;
- u32 hpu2apu_irq_ack;
+ u32 apu2hpu_irq_ack;
u32 reserved13[13];
u32 ppu2apu_mb_offset;
u32 ppu2apu_irq;
- u32 ppu2apu_irq_ack;
+ u32 apu2ppu_irq_ack;
u32 reserved14[13];
u32 epu2apu_mb_offset;
u32 epu2apu_irq;
- u32 epu2apu_irq_ack;
+ u32 apu2epu_irq_ack;
u32 reserved15[13];
u32 reserved16[8];
@@ -178,22 +178,22 @@ struct cx18_scb {
u32 reserved21[7];
u32 cpu2hpu_mb_offset;
u32 cpu2hpu_irq;
- u32 cpu2hpu_irq_ack;
+ u32 hpu2cpu_irq_ack;
u32 reserved22[13];
u32 apu2hpu_mb_offset;
u32 apu2hpu_irq;
- u32 apu2hpu_irq_ack;
+ u32 hpu2apu_irq_ack;
u32 reserved23[13];
u32 ppu2hpu_mb_offset;
u32 ppu2hpu_irq;
- u32 ppu2hpu_irq_ack;
+ u32 hpu2ppu_irq_ack;
u32 reserved24[13];
u32 epu2hpu_mb_offset;
u32 epu2hpu_irq;
- u32 epu2hpu_irq_ack;
+ u32 hpu2epu_irq_ack;
u32 reserved25[13];
u32 reserved26[8];
@@ -203,22 +203,22 @@ struct cx18_scb {
u32 reserved31[7];
u32 cpu2ppu_mb_offset;
u32 cpu2ppu_irq;
- u32 cpu2ppu_irq_ack;
+ u32 ppu2cpu_irq_ack;
u32 reserved32[13];
u32 apu2ppu_mb_offset;
u32 apu2ppu_irq;
- u32 apu2ppu_irq_ack;
+ u32 ppu2apu_irq_ack;
u32 reserved33[13];
u32 hpu2ppu_mb_offset;
u32 hpu2ppu_irq;
- u32 hpu2ppu_irq_ack;
+ u32 ppu2hpu_irq_ack;
u32 reserved34[13];
u32 epu2ppu_mb_offset;
u32 epu2ppu_irq;
- u32 epu2ppu_irq_ack;
+ u32 ppu2epu_irq_ack;
u32 reserved35[13];
u32 reserved36[8];
@@ -228,22 +228,22 @@ struct cx18_scb {
u32 reserved41[7];
u32 cpu2epu_mb_offset;
u32 cpu2epu_irq;
- u32 cpu2epu_irq_ack;
+ u32 epu2cpu_irq_ack;
u32 reserved42[13];
u32 apu2epu_mb_offset;
u32 apu2epu_irq;
- u32 apu2epu_irq_ack;
+ u32 epu2apu_irq_ack;
u32 reserved43[13];
u32 hpu2epu_mb_offset;
u32 hpu2epu_irq;
- u32 hpu2epu_irq_ack;
+ u32 epu2hpu_irq_ack;
u32 reserved44[13];
u32 ppu2epu_mb_offset;
u32 ppu2epu_irq;
- u32 ppu2epu_irq_ack;
+ u32 epu2ppu_irq_ack;
u32 reserved45[13];
u32 reserved46[8];
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