diff options
Diffstat (limited to 'drivers/pinctrl/sunxi')
| -rw-r--r-- | drivers/pinctrl/sunxi/Kconfig | 57 | ||||
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.c | 96 | ||||
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.h | 18 |
6 files changed, 119 insertions, 57 deletions
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index a731fc966b63..9093a420d310 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -11,82 +11,101 @@ config PINCTRL_SUNIV_F1C100S select PINCTRL_SUNXI config PINCTRL_SUN4I_A10 - def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I + bool "Support for the Allwinner A10, A20 and R40 PIO" + default MACH_SUN4I || MACH_SUN7I || MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN5I - def_bool MACH_SUN5I + bool "Support for the Allwinner A10s, A13, R8 and NextThing GR8 PIO" + default MACH_SUN5I select PINCTRL_SUNXI config PINCTRL_SUN6I_A31 - def_bool MACH_SUN6I + bool "Support for the Allwinner A31 PIO" + default MACH_SUN6I select PINCTRL_SUNXI config PINCTRL_SUN6I_A31_R - def_bool MACH_SUN6I + bool "Support for the Allwinner A31 R-PIO" + default MACH_SUN6I depends on RESET_CONTROLLER select PINCTRL_SUNXI config PINCTRL_SUN8I_A23 - def_bool MACH_SUN8I + bool "Support for the Allwinner A23 PIO" + default MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN8I_A33 - def_bool MACH_SUN8I + bool "Support for the Allwinner A33 PIO" + default MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN8I_A83T - def_bool MACH_SUN8I + bool "Support for the Allwinner A83T PIO" + default MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN8I_A83T_R - def_bool MACH_SUN8I + bool "Support for the Allwinner A83T R-PIO" + default MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN8I_A23_R - def_bool MACH_SUN8I + bool "Support for the Allwinner A23 and A33 R-PIO" + default MACH_SUN8I depends on RESET_CONTROLLER select PINCTRL_SUNXI config PINCTRL_SUN8I_H3 - def_bool MACH_SUN8I + bool "Support for the Allwinner H3 PIO" + default MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN8I_H3_R - def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI) + bool "Support for the Allwinner H3 and H5 R-PIO" + default MACH_SUN8I || (ARM64 && ARCH_SUNXI) select PINCTRL_SUNXI config PINCTRL_SUN8I_V3S - def_bool MACH_SUN8I + bool "Support for the Allwinner V3s PIO" + default MACH_SUN8I select PINCTRL_SUNXI config PINCTRL_SUN9I_A80 - def_bool MACH_SUN9I + bool "Support for the Allwinner A80 PIO" + default MACH_SUN9I select PINCTRL_SUNXI config PINCTRL_SUN9I_A80_R - def_bool MACH_SUN9I + bool "Support for the Allwinner A80 R-PIO" + default MACH_SUN9I depends on RESET_CONTROLLER select PINCTRL_SUNXI config PINCTRL_SUN50I_A64 - def_bool ARM64 && ARCH_SUNXI + bool "Support for the Allwinner A64 PIO" + default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI config PINCTRL_SUN50I_A64_R - def_bool ARM64 && ARCH_SUNXI + bool "Support for the Allwinner A64 R-PIO" + default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI config PINCTRL_SUN50I_H5 - def_bool ARM64 && ARCH_SUNXI + bool "Support for the Allwinner H5 PIO" + default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI config PINCTRL_SUN50I_H6 - def_bool ARM64 && ARCH_SUNXI + bool "Support for the Allwinner H6 PIO" + default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI config PINCTRL_SUN50I_H6_R - def_bool ARM64 && ARCH_SUNXI + bool "Support for the Allwinner H6 R-PIO" + default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI endif diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c index ef4268cc6227..3cc1121589c9 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c @@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = { .irq_banks = 4, .irq_bank_map = h6_irq_bank_map, .irq_read_needs_mux = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, }; static int h6_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c index e05dd9a5551d..a191a65217ac 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c @@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = { .pin_base = PL_BASE, .irq_banks = 2, .disable_strict_mode = true, - .has_io_bias_cfg = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, }; static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index da37d594a13d..0633a03d5e13 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { .npins = ARRAY_SIZE(sun9i_a80_pins), .irq_banks = 5, .disable_strict_mode = true, - .has_io_bias_cfg = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, }; static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 8dd25caea2cf..0cbca30b75dc 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -530,14 +530,10 @@ static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, return sunxi_pconf_get(pctldev, g->pin, config); } -static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, - unsigned group, - unsigned long *configs, - unsigned num_configs) +static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *configs, unsigned num_configs) { struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); - struct sunxi_pinctrl_group *g = &pctl->groups[group]; - unsigned pin = g->pin - pctl->desc->pin_base; int i; for (i = 0; i < num_configs; i++) { @@ -596,9 +592,20 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, return 0; } +static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, + unsigned long *configs, unsigned num_configs) +{ + struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct sunxi_pinctrl_group *g = &pctl->groups[group]; + + /* We only support 1 pin per group. Chain it to the pin callback */ + return sunxi_pconf_set(pctldev, g->pin, configs, num_configs); +} + static const struct pinconf_ops sunxi_pconf_ops = { .is_generic = true, .pin_config_get = sunxi_pconf_get, + .pin_config_set = sunxi_pconf_set, .pin_config_group_get = sunxi_pconf_group_get, .pin_config_group_set = sunxi_pconf_group_set, }; @@ -607,10 +614,12 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, unsigned pin, struct regulator *supply) { + unsigned short bank = pin / PINS_PER_BANK; + unsigned long flags; u32 val, reg; int uV; - if (!pctl->desc->has_io_bias_cfg) + if (!pctl->desc->io_bias_cfg_variant) return 0; uV = regulator_get_voltage(supply); @@ -621,25 +630,41 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, if (uV == 0) return 0; - /* Configured value must be equal or greater to actual voltage */ - if (uV <= 1800000) - val = 0x0; /* 1.8V */ - else if (uV <= 2500000) - val = 0x6; /* 2.5V */ - else if (uV <= 2800000) - val = 0x9; /* 2.8V */ - else if (uV <= 3000000) - val = 0xA; /* 3.0V */ - else - val = 0xD; /* 3.3V */ - - pin -= pctl->desc->pin_base; - - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); - reg &= ~IO_BIAS_MASK; - writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + switch (pctl->desc->io_bias_cfg_variant) { + case BIAS_VOLTAGE_GRP_CONFIG: + /* + * Configured value must be equal or greater to actual + * voltage. + */ + if (uV <= 1800000) + val = 0x0; /* 1.8V */ + else if (uV <= 2500000) + val = 0x6; /* 2.5V */ + else if (uV <= 2800000) + val = 0x9; /* 2.8V */ + else if (uV <= 3000000) + val = 0xA; /* 3.0V */ + else + val = 0xD; /* 3.3V */ + + pin -= pctl->desc->pin_base; + + reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); + reg &= ~IO_BIAS_MASK; + writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + return 0; + case BIAS_VOLTAGE_PIO_POW_MODE_SEL: + val = uV <= 1800000 ? 1 : 0; - return 0; + raw_spin_lock_irqsave(&pctl->lock, flags); + reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); + reg &= ~(1 << bank); + writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); + raw_spin_unlock_irqrestore(&pctl->lock, flags); + return 0; + default: + return -EINVAL; + } } static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) @@ -1443,16 +1468,17 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; pctl->chip->owner = THIS_MODULE; - pctl->chip->request = gpiochip_generic_request, - pctl->chip->free = gpiochip_generic_free, - pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input, - pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output, - pctl->chip->get = sunxi_pinctrl_gpio_get, - pctl->chip->set = sunxi_pinctrl_gpio_set, - pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate, - pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq, - pctl->chip->of_gpio_n_cells = 3, - pctl->chip->can_sleep = false, + pctl->chip->request = gpiochip_generic_request; + pctl->chip->free = gpiochip_generic_free; + pctl->chip->set_config = gpiochip_generic_config; + pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input; + pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output; + pctl->chip->get = sunxi_pinctrl_gpio_get; + pctl->chip->set = sunxi_pinctrl_gpio_set; + pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate; + pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq; + pctl->chip->of_gpio_n_cells = 3; + pctl->chip->can_sleep = false; pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - pctl->desc->pin_base; pctl->chip->label = dev_name(&pdev->dev); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index ee15ab067b5f..44e30deeee38 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -95,6 +95,22 @@ #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +#define PIO_POW_MOD_SEL_REG 0x340 + +enum sunxi_desc_bias_voltage { + BIAS_VOLTAGE_NONE, + /* + * Bias voltage configuration is done through + * Pn_GRP_CONFIG registers, as seen on A80 SoC. + */ + BIAS_VOLTAGE_GRP_CONFIG, + /* + * Bias voltage is set through PIO_POW_MOD_SEL_REG + * register, as seen on H6 SoC, for example. + */ + BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + struct sunxi_desc_function { unsigned long variant; const char *name; @@ -117,7 +133,7 @@ struct sunxi_pinctrl_desc { const unsigned int *irq_bank_map; bool irq_read_needs_mux; bool disable_strict_mode; - bool has_io_bias_cfg; + enum sunxi_desc_bias_voltage io_bias_cfg_variant; }; struct sunxi_pinctrl_function { |
