diff options
Diffstat (limited to 'drivers/clk/samsung')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 14 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 30 |
2 files changed, 22 insertions, 22 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 8c8b495cbf0d..cdc092a1d9ef 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -586,7 +586,7 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", GATE_BUS_TOP, 24, 0, 0), GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", - GATE_BUS_TOP, 27, 0, 0), + GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), }; static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { @@ -956,20 +956,20 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", - GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), + GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", - GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), + GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", GATE_BUS_TOP, 5, 0, 0), GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", - GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), + GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", @@ -983,20 +983,20 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(0, "aclk166", "mout_user_aclk166", GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", - GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), + GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE_BUS_TOP, 16, 0, 0), GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", GATE_BUS_TOP, 17, 0, 0), GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", - GATE_BUS_TOP, 18, 0, 0), + GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", GATE_BUS_TOP, 28, 0, 0), GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", GATE_BUS_TOP, 29, 0, 0), GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", - SRC_MASK_TOP2, 24, 0, 0), + SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", SRC_MASK_TOP7, 20, 0, 0), diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index ea1608682d7f..f096bd7df40c 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -543,7 +543,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { static const struct samsung_gate_clock top_gate_clks[] __initconst = { /* ENABLE_ACLK_TOP */ GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", - ENABLE_ACLK_TOP, 30, 0, 0), + ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266", "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, 29, CLK_IGNORE_UNUSED, 0), @@ -555,25 +555,25 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", ENABLE_ACLK_TOP, 24, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200", ENABLE_ACLK_TOP, 23, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", ENABLE_ACLK_TOP, 22, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", ENABLE_ACLK_TOP, 21, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400", ENABLE_ACLK_TOP, 19, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", ENABLE_ACLK_TOP, 18, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", ENABLE_ACLK_TOP, 15, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", ENABLE_ACLK_TOP, 14, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), @@ -582,7 +582,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400", ENABLE_ACLK_TOP, 12, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552", ENABLE_ACLK_TOP, 11, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), @@ -591,7 +591,7 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400", ENABLE_ACLK_TOP, 9, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552", ENABLE_ACLK_TOP, 8, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), @@ -600,19 +600,19 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", ENABLE_ACLK_TOP, 6, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", ENABLE_ACLK_TOP, 5, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", ENABLE_ACLK_TOP, 3, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", ENABLE_ACLK_TOP, 2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", ENABLE_ACLK_TOP, 0, - CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0), /* ENABLE_SCLK_TOP_MSCL */ GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", @@ -1385,7 +1385,7 @@ static const struct samsung_gate_clock mif_gate_clks[] __initconst = { CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", ENABLE_ACLK_MIF3, 1, - CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", ENABLE_ACLK_MIF3, 0, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), @@ -1929,7 +1929,7 @@ CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", /* list of all parent clock list */ PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; -PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; +PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", }; PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; |
