diff options
Diffstat (limited to 'arch/arm')
22 files changed, 289 insertions, 92 deletions
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h index 31fb2e68d527..203dd5a18bd5 100644 --- a/arch/arm/mach-s5p6442/include/mach/map.h +++ b/arch/arm/mach-s5p6442/include/mach/map.h @@ -28,6 +28,9 @@ #define S5P6442_PA_VIC1 (0xE4100000) #define S5P6442_PA_VIC2 (0xE4200000) +#define S5P6442_PA_SROMC (0xE7000000) +#define S5P_PA_SROMC S5P6442_PA_SROMC + #define S5P6442_PA_MDMA 0xE8000000 #define S5P6442_PA_PDMA 0xE9000000 diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h index 4d3d332152d0..a9365e5ba614 100644 --- a/arch/arm/mach-s5p64x0/include/mach/map.h +++ b/arch/arm/mach-s5p64x0/include/mach/map.h @@ -29,6 +29,9 @@ #define S5P64X0_PA_VIC0 (0xE4000000) #define S5P64X0_PA_VIC1 (0xE4100000) +#define S5P64X0_PA_SROMC (0xE7000000) +#define S5P_PA_SROMC S5P64X0_PA_SROMC + #define S5P64X0_PA_PDMA (0xE9000000) #define S5P64X0_PA_TIMER (0xEA000000) diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 32e9cab5c864..328467b346aa 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -55,6 +55,8 @@ #define S5PC100_VA_VIC_OFFSET 0x10000 #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) +#define S5PC100_PA_SROMC (0xE7000000) +#define S5P_PA_SROMC S5PC100_PA_SROMC #define S5PC100_PA_ONENAND (0xE7100000) diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index b774ff1805db..dab6ef3b6ca9 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c @@ -525,6 +525,12 @@ static struct clk init_clocks[] = { .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, .ctrlbit = (1 << 20), + }, { + .name = "sromc", + .id = -1, + .parent = &clk_hclk_psys.clk, + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 26), }, }; diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 8eb480e201b0..61e6c24b90ac 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c @@ -81,11 +81,6 @@ static struct map_desc s5pv210_iodesc[] __initdata = { .length = SZ_512K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S5P_VA_SROMC, - .pfn = __phys_to_pfn(S5PV210_PA_SROMC), - .length = SZ_4K, - .type = MT_DEVICE, - }, { .virtual = (unsigned long)S5P_VA_DMC0, .pfn = __phys_to_pfn(S5PV210_PA_DMC0), .length = SZ_4K, diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 119b95fdc3ce..26710b35ef87 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h @@ -65,7 +65,7 @@ #define IRQ_HSMMC0 S5P_IRQ_VIC1(26) #define IRQ_HSMMC1 S5P_IRQ_VIC1(27) #define IRQ_HSMMC2 S5P_IRQ_VIC1(28) -#define IRQ_MIPICSI S5P_IRQ_VIC1(29) +#define IRQ_MIPI_CSIS S5P_IRQ_VIC1(29) #define IRQ_MIPIDSI S5P_IRQ_VIC1(30) #define IRQ_ONENAND_AUDI S5P_IRQ_VIC1(31) @@ -132,5 +132,6 @@ #define IRQ_LCD_FIFO IRQ_LCD0 #define IRQ_LCD_VSYNC IRQ_LCD1 #define IRQ_LCD_SYSTEM IRQ_LCD2 +#define IRQ_MIPI_CSIS0 IRQ_MIPI_CSIS #endif /* ASM_ARCH_IRQS_H */ diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 861d7fe11fc9..3611492ad681 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h @@ -16,6 +16,8 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> +#define S5PV210_PA_SROM_BANK5 (0xA8000000) + #define S5PC110_PA_ONENAND (0xB0000000) #define S5P_PA_ONENAND S5PC110_PA_ONENAND @@ -60,6 +62,7 @@ #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #define S5PV210_PA_SROMC (0xE8000000) +#define S5P_PA_SROMC S5PV210_PA_SROMC #define S5PV210_PA_CFCON (0xE8200000) @@ -107,6 +110,8 @@ #define S5PV210_PA_DMC0 (0xF0000000) #define S5PV210_PA_DMC1 (0xF1400000) +#define S5PV210_PA_MIPI_CSIS 0xFA600000 + /* compatibiltiy defines. */ #define S3C_PA_UART S5PV210_PA_UART #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) @@ -123,6 +128,7 @@ #define S5P_PA_FIMC0 S5PV210_PA_FIMC0 #define S5P_PA_FIMC1 S5PV210_PA_FIMC1 #define S5P_PA_FIMC2 S5PV210_PA_FIMC2 +#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS #define SAMSUNG_PA_ADC S5PV210_PA_ADC #define SAMSUNG_PA_CFCON S5PV210_PA_CFCON diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index ebaabe021af9..4c45b74def5f 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -161,7 +161,7 @@ #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) -#define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) +#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814) #define S5P_IDLE_CFG_TL_MASK (3 << 30) #define S5P_IDLE_CFG_TM_MASK (3 << 28) @@ -195,9 +195,6 @@ #define S5P_OTHERS_RET_UART (1 << 28) #define S5P_OTHERS_USB_SIG_MASK (1 << 16) -/* MIPI */ -#define S5P_MIPI_DPHY_EN (3) - /* S5P_DAC_CONTROL */ #define S5P_DAC_ENABLE (1) #define S5P_DAC_DISABLE (0) diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 82e635625073..3a59068e983a 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c @@ -14,6 +14,8 @@ #include <linux/init.h> #include <linux/serial_core.h> #include <linux/sysdev.h> +#include <linux/dm9000.h> +#include <linux/gpio.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -24,6 +26,8 @@ #include <mach/regs-clock.h> #include <plat/regs-serial.h> +#include <plat/regs-srom.h> +#include <plat/gpio-cfg.h> #include <plat/s5pv210.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -102,6 +106,39 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = { .cols = 8, }; +static struct resource smdkv210_dm9000_resources[] = { + [0] = { + .start = S5PV210_PA_SROM_BANK5, + .end = S5PV210_PA_SROM_BANK5, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = S5PV210_PA_SROM_BANK5 + 2, + .end = S5PV210_PA_SROM_BANK5 + 2, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_EINT(9), + .end = IRQ_EINT(9), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct dm9000_plat_data smdkv210_dm9000_platdata = { + .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM, + .dev_addr = { 0x00, 0x09, 0xc0, 0xff, 0xec, 0x48 }, +}; + +struct platform_device smdkv210_dm9000 = { + .name = "dm9000", + .id = -1, + .num_resources = ARRAY_SIZE(smdkv210_dm9000_resources), + .resource = smdkv210_dm9000_resources, + .dev = { + .platform_data = &smdkv210_dm9000_platdata, + }, +}; + static struct platform_device *smdkv210_devices[] __initdata = { &s5pv210_device_iis0, &s5pv210_device_ac97, @@ -119,8 +156,26 @@ static struct platform_device *smdkv210_devices[] __initdata = { &s3c_device_rtc, &s3c_device_ts, &s3c_device_wdt, + &smdkv210_dm9000, }; +static void __init smdkv210_dm9000_init(void) +{ + unsigned int tmp; + + gpio_request(S5PV210_MP01(5), "nCS5"); + s3c_gpio_cfgpin(S5PV210_MP01(5), S3C_GPIO_SFN(2)); + gpio_free(S5PV210_MP01(5)); + + tmp = (5 << S5P_SROM_BCX__TACC__SHIFT); + __raw_writel(tmp, S5P_SROM_BC5); + + tmp = __raw_readl(S5P_SROM_BW); + tmp &= (S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS5__SHIFT); + tmp |= (1 << S5P_SROM_BW__NCS5__SHIFT); + __raw_writel(tmp, S5P_SROM_BW); +} + static struct i2c_board_info smdkv210_i2c_devs0[] __initdata = { { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung S524AD0XD1 */ { I2C_BOARD_INFO("wm8580", 0x1b), }, @@ -151,6 +206,8 @@ static void __init smdkv210_machine_init(void) { s3c_pm_init(); + smdkv210_dm9000_init(); + samsung_keypad_set_platdata(&smdkv210_keypad_data); s3c24xx_ts_set_platdata(&s3c_ts_platform); diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h index 3c05c58b5392..34f214444f27 100644 --- a/arch/arm/mach-s5pv310/include/mach/irqs.h +++ b/arch/arm/mach-s5pv310/include/mach/irqs.h @@ -86,6 +86,9 @@ #define IRQ_HSMMC2 COMBINER_IRQ(29, 2) #define IRQ_HSMMC3 COMBINER_IRQ(29, 3) +#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0) +#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1) + #define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0) #define IRQ_EINT4 COMBINER_IRQ(37, 0) diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 53994467605d..0d0e7eb5b391 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h @@ -61,9 +61,13 @@ #define S5PV310_PA_GPIO2 (0x11000000) #define S5PV310_PA_GPIO3 (0x03860000) +#define S5PV310_PA_MIPI_CSIS0 0x11880000 +#define S5PV310_PA_MIPI_CSIS1 0x11890000 + #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) #define S5PV310_PA_SROMC (0x12570000) +#define S5P_PA_SROMC S5PV310_PA_SROMC /* S/PDIF */ #define S5PV310_PA_SPDIF 0xE1100000 @@ -116,5 +120,7 @@ #define S3C_PA_IIC7 S5PV310_PA_IIC(7) #define S3C_PA_RTC S5PV310_PA_RTC #define S3C_PA_WDT S5PV310_PA_WATCHDOG +#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0 +#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1 #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5pv310/include/mach/regs-srom.h b/arch/arm/mach-s5pv310/include/mach/regs-srom.h deleted file mode 100644 index 1898b3e10550..000000000000 --- a/arch/arm/mach-s5pv310/include/mach/regs-srom.h +++ /dev/null @@ -1,50 +0,0 @@ -/* linux/arch/arm/mach-s5pv310/include/mach/regs-srom.h - * - * Copyright (c) 2010 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * S5PV310 - SROMC register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_SROM_H -#define __ASM_ARCH_REGS_SROM_H __FILE__ - -#include <mach/map.h> - -#define S5PV310_SROMREG(x) (S5P_VA_SROMC + (x)) - -#define S5PV310_SROM_BW S5PV310_SROMREG(0x0) -#define S5PV310_SROM_BC0 S5PV310_SROMREG(0x4) -#define S5PV310_SROM_BC1 S5PV310_SROMREG(0x8) -#define S5PV310_SROM_BC2 S5PV310_SROMREG(0xc) -#define S5PV310_SROM_BC3 S5PV310_SROMREG(0x10) - -/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ - -#define S5PV310_SROM_BW__DATAWIDTH__SHIFT 0 -#define S5PV310_SROM_BW__ADDRMODE__SHIFT 1 -#define S5PV310_SROM_BW__WAITENABLE__SHIFT 2 -#define S5PV310_SROM_BW__BYTEENABLE__SHIFT 3 - -#define S5PV310_SROM_BW__CS_MASK 0xf - -#define S5PV310_SROM_BW__NCS0__SHIFT 0 -#define S5PV310_SROM_BW__NCS1__SHIFT 4 -#define S5PV310_SROM_BW__NCS2__SHIFT 8 -#define S5PV310_SROM_BW__NCS3__SHIFT 12 - -/* applies to same to BCS0 - BCS3 */ - -#define S5PV310_SROM_BCX__PMC__SHIFT 0 -#define S5PV310_SROM_BCX__TACP__SHIFT 4 -#define S5PV310_SROM_BCX__TCAH__SHIFT 8 -#define S5PV310_SROM_BCX__TCOH__SHIFT 12 -#define S5PV310_SROM_BCX__TACC__SHIFT 16 -#define S5PV310_SROM_BCX__TCOS__SHIFT 24 -#define S5PV310_SROM_BCX__TACS__SHIFT 28 - -#endif /* __ASM_ARCH_REGS_SROM_H */ diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-s5pv310/mach-smdkc210.c index 62c4d6204d2a..f3bc283df119 100644 --- a/arch/arm/mach-s5pv310/mach-smdkc210.c +++ b/arch/arm/mach-s5pv310/mach-smdkc210.c @@ -20,6 +20,7 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/regs-srom.h> #include <plat/s5pv310.h> #include <plat/cpu.h> #include <plat/devs.h> @@ -27,7 +28,6 @@ #include <plat/iic.h> #include <mach/map.h> -#include <mach/regs-srom.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -163,23 +163,22 @@ static void __init smdkc210_smsc911x_init(void) u32 cs1; /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5PV310_SROM_BW) & - ~(S5PV310_SROM_BW__CS_MASK << - S5PV310_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << - S5PV310_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5PV310_SROM_BW); + cs1 = __raw_readl(S5P_SROM_BW) & + ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | + (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << + S5P_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S5P_SROM_BW); /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | - (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | - (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); + __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | + (0x9 << S5P_SROM_BCX__TACP__SHIFT) | + (0xc << S5P_SROM_BCX__TCAH__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | + (0x6 << S5P_SROM_BCX__TACC__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | + (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); } static void __init smdkc210_map_io(void) diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c index d5eb607763f7..e4a826ac3c1d 100644 --- a/arch/arm/mach-s5pv310/mach-smdkv310.c +++ b/arch/arm/mach-s5pv310/mach-smdkv310.c @@ -20,6 +20,7 @@ #include <asm/mach-types.h> #include <plat/regs-serial.h> +#include <plat/regs-srom.h> #include <plat/s5pv310.h> #include <plat/cpu.h> #include <plat/devs.h> @@ -27,7 +28,6 @@ #include <plat/iic.h> #include <mach/map.h> -#include <mach/regs-srom.h> /* Following are default values for UCON, ULCON and UFCON UART registers */ #define SMDKV310_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ @@ -163,23 +163,22 @@ static void __init smdkv310_smsc911x_init(void) u32 cs1; /* configure nCS1 width to 16 bits */ - cs1 = __raw_readl(S5PV310_SROM_BW) & - ~(S5PV310_SROM_BW__CS_MASK << - S5PV310_SROM_BW__NCS1__SHIFT); - cs1 |= ((1 << S5PV310_SROM_BW__DATAWIDTH__SHIFT) | - (1 << S5PV310_SROM_BW__WAITENABLE__SHIFT) | - (1 << S5PV310_SROM_BW__BYTEENABLE__SHIFT)) << - S5PV310_SROM_BW__NCS1__SHIFT; - __raw_writel(cs1, S5PV310_SROM_BW); + cs1 = __raw_readl(S5P_SROM_BW) & + ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S5P_SROM_BW__WAITENABLE__SHIFT) | + (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) << + S5P_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S5P_SROM_BW); /* set timing for nCS1 suitable for ethernet chip */ - __raw_writel((0x1 << S5PV310_SROM_BCX__PMC__SHIFT) | - (0x9 << S5PV310_SROM_BCX__TACP__SHIFT) | - (0xc << S5PV310_SROM_BCX__TCAH__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOH__SHIFT) | - (0x6 << S5PV310_SROM_BCX__TACC__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TCOS__SHIFT) | - (0x1 << S5PV310_SROM_BCX__TACS__SHIFT), S5PV310_SROM_BC1); + __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) | + (0x9 << S5P_SROM_BCX__TACP__SHIFT) | + (0xc << S5P_SROM_BCX__TCAH__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOH__SHIFT) | + (0x6 << S5P_SROM_BCX__TACC__SHIFT) | + (0x1 << S5P_SROM_BCX__TCOS__SHIFT) | + (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1); } static void __init smdkv310_map_io(void) diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 65dbfa8e0a86..6a161f317a79 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig @@ -56,3 +56,13 @@ config S5P_DEV_ONENAND bool help Compile in platform device definition for OneNAND controller + +config S5P_DEV_CSIS0 + bool + help + Compile in platform device definitions for MIPI-CSIS channel 0 + +config S5P_DEV_CSIS1 + bool + help + Compile in platform device definitions for MIPI-CSIS channel 1 diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index de65238a7aef..2b7317378103 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile @@ -28,3 +28,5 @@ obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o +obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o +obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index 74f7f5a5446c..047d31c1bbd8 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c @@ -108,6 +108,11 @@ static struct map_desc s5p_iodesc[] __initdata = { .pfn = __phys_to_pfn(S3C_PA_WDT), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SROMC, + .pfn = __phys_to_pfn(S5P_PA_SROMC), + .length = SZ_4K, + .type = MT_DEVICE, }, }; diff --git a/arch/arm/plat-s5p/dev-csis0.c b/arch/arm/plat-s5p/dev-csis0.c new file mode 100644 index 000000000000..dfab1c85f54f --- /dev/null +++ b/arch/arm/plat-s5p/dev-csis0.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series device definition for MIPI-CSIS channel 0 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <mach/map.h> + +static struct resource s5p_mipi_csis0_resource[] = { + [0] = { + .start = S5P_PA_MIPI_CSIS0, + .end = S5P_PA_MIPI_CSIS0 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MIPI_CSIS0, + .end = IRQ_MIPI_CSIS0, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device s5p_device_mipi_csis0 = { + .name = "s5p-mipi-csis", + .id = 0, + .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource), + .resource = s5p_mipi_csis0_resource, +}; diff --git a/arch/arm/plat-s5p/dev-csis1.c b/arch/arm/plat-s5p/dev-csis1.c new file mode 100644 index 000000000000..e3053f27fbbf --- /dev/null +++ b/arch/arm/plat-s5p/dev-csis1.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series device definition for MIPI-CSIS channel 1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <mach/map.h> + +static struct resource s5p_mipi_csis1_resource[] = { + [0] = { + .start = S5P_PA_MIPI_CSIS1, + .end = S5P_PA_MIPI_CSIS1 + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_MIPI_CSIS1, + .end = IRQ_MIPI_CSIS1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s5p_device_mipi_csis1 = { + .name = "s5p-mipi-csis", + .id = 1, + .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource), + .resource = s5p_mipi_csis1_resource, +}; diff --git a/arch/arm/plat-s5p/include/plat/csis.h b/arch/arm/plat-s5p/include/plat/csis.h new file mode 100644 index 000000000000..51e308c7981d --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/csis.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * + * S5P series MIPI CSI slave device support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef PLAT_S5P_CSIS_H_ +#define PLAT_S5P_CSIS_H_ __FILE__ + +/** + * struct s5p_platform_mipi_csis - platform data for MIPI-CSIS + * @clk_rate: bus clock frequency + * @lanes: number of data lanes used + * @alignment: data alignment in bits + * @hs_settle: HS-RX settle time + */ +struct s5p_platform_mipi_csis { + unsigned long clk_rate; + u8 lanes; + u8 alignment; + u8 hs_settle; +}; + +#endif /* PLAT_S5P_CSIS_H_ */ diff --git a/arch/arm/plat-s5p/include/plat/regs-srom.h b/arch/arm/plat-s5p/include/plat/regs-srom.h new file mode 100644 index 000000000000..f121ab5e76cb --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/regs-srom.h @@ -0,0 +1,54 @@ +/* linux/arch/arm/plat-s5p/include/plat/regs-srom.h + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * S5P SROMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_REGS_SROM_H +#define __ASM_PLAT_S5P_REGS_SROM_H __FILE__ + +#include <mach/map.h> + +#define S5P_SROMREG(x) (S5P_VA_SROMC + (x)) + +#define S5P_SROM_BW S5P_SROMREG(0x0) +#define S5P_SROM_BC0 S5P_SROMREG(0x4) +#define S5P_SROM_BC1 S5P_SROMREG(0x8) +#define S5P_SROM_BC2 S5P_SROMREG(0xc) +#define S5P_SROM_BC3 S5P_SROMREG(0x10) +#define S5P_SROM_BC4 S5P_SROMREG(0x14) +#define S5P_SROM_BC5 S5P_SROMREG(0x18) + +/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ + +#define S5P_SROM_BW__DATAWIDTH__SHIFT 0 +#define S5P_SROM_BW__ADDRMODE__SHIFT 1 +#define S5P_SROM_BW__WAITENABLE__SHIFT 2 +#define S5P_SROM_BW__BYTEENABLE__SHIFT 3 + +#define S5P_SROM_BW__CS_MASK 0xf + +#define S5P_SROM_BW__NCS0__SHIFT 0 +#define S5P_SROM_BW__NCS1__SHIFT 4 +#define S5P_SROM_BW__NCS2__SHIFT 8 +#define S5P_SROM_BW__NCS3__SHIFT 12 +#define S5P_SROM_BW__NCS4__SHIFT 16 +#define S5P_SROM_BW__NCS5__SHIFT 20 + +/* applies to same to BCS0 - BCS3 */ + +#define S5P_SROM_BCX__PMC__SHIFT 0 +#define S5P_SROM_BCX__TACP__SHIFT 4 +#define S5P_SROM_BCX__TCAH__SHIFT 8 +#define S5P_SROM_BCX__TCOH__SHIFT 12 +#define S5P_SROM_BCX__TACC__SHIFT 16 +#define S5P_SROM_BCX__TCOS__SHIFT 24 +#define S5P_SROM_BCX__TACS__SHIFT 28 + +#endif /* __ASM_PLAT_S5P_REGS_SROM_H */ diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 126196e9983b..94794c816b0e 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h @@ -133,6 +133,9 @@ extern struct platform_device s5p_device_fimc0; extern struct platform_device s5p_device_fimc1; extern struct platform_device s5p_device_fimc2; +extern struct platform_device s5p_device_mipi_csis0; +extern struct platform_device s5p_device_mipi_csis1; + /* s3c2440 specific devices */ #ifdef CONFIG_CPU_S3C2440 |
