diff options
Diffstat (limited to 'arch/arm/mach-mmp/include')
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/addr-map.h | 12 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/devices.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/entry-macro.S | 4 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/irqs.h | 27 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/pm-mmp2.h | 61 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/pm-pxa910.h | 77 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/pxa168.h | 8 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/pxa910.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apbc.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apmu.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-usb.h | 253 |
11 files changed, 434 insertions, 20 deletions
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h index b1ece08174e8..f88a44c0ef91 100644 --- a/arch/arm/mach-mmp/include/mach/addr-map.h +++ b/arch/arm/mach-mmp/include/mach/addr-map.h @@ -31,4 +31,16 @@ #define SMC_CS1_PHYS_BASE 0x90000000 #define SMC_CS1_PHYS_SIZE 0x10000000 +#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) +#define APMU_REG(x) (APMU_VIRT_BASE + (x)) + +#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) +#define APBC_REG(x) (APBC_VIRT_BASE + (x)) + +#define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) +#define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) + +#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) +#define CIU_REG(x) (CIU_VIRT_BASE + (x)) + #endif /* __ASM_MACH_ADDR_MAP_H */ diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h index d0ec7dae88e4..21217ef11b64 100644 --- a/arch/arm/mach-mmp/include/mach/devices.h +++ b/arch/arm/mach-mmp/include/mach/devices.h @@ -50,4 +50,7 @@ struct pxa_device_desc mmp2_device_##_name __initdata = { \ } extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); +extern int pxa_usb_phy_init(void __iomem *phy_reg); +extern void pxa_usb_phy_deinit(void __iomem *phy_reg); + #endif /* __MACH_DEVICE_H */ diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S index 9cff9e7a2b26..bd152e24e6d7 100644 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S @@ -6,13 +6,15 @@ * published by the Free Software Foundation. */ +#include <asm/irq.h> #include <mach/regs-icu.h> .macro get_irqnr_preamble, base, tmp mrc p15, 0, \tmp, c0, c0, 0 @ CPUID and \tmp, \tmp, #0xff00 cmp \tmp, #0x5800 - ldr \base, =ICU_VIRT_BASE + ldr \base, =mmp_icu_base + ldr \base, [\base, #0] addne \base, \base, #0x10c @ PJ1 AP INT SEL register addeq \base, \base, #0x104 @ PJ4 IRQ SEL register .endm diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index d0e746626a3d..fb492a50a817 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -125,7 +125,7 @@ #define IRQ_MMP2_RTC_MUX 5 #define IRQ_MMP2_TWSI1 7 #define IRQ_MMP2_GPU 8 -#define IRQ_MMP2_KEYPAD 9 +#define IRQ_MMP2_KEYPAD_MUX 9 #define IRQ_MMP2_ROTARY 10 #define IRQ_MMP2_TRACKBALL 11 #define IRQ_MMP2_ONEWIRE 12 @@ -163,11 +163,11 @@ #define IRQ_MMP2_DMA_FIQ 47 #define IRQ_MMP2_DMA_RIQ 48 #define IRQ_MMP2_GPIO 49 -#define IRQ_MMP2_SSP_MUX 51 +#define IRQ_MMP2_MIPI_HSI1_MUX 51 #define IRQ_MMP2_MMC2 52 #define IRQ_MMP2_MMC3 53 #define IRQ_MMP2_MMC4 54 -#define IRQ_MMP2_MIPI_HSI 55 +#define IRQ_MMP2_MIPI_HSI0_MUX 55 #define IRQ_MMP2_MSP 58 #define IRQ_MMP2_MIPI_SLIM_DMA 59 #define IRQ_MMP2_PJ4_FREQ_CHG 60 @@ -186,8 +186,14 @@ #define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) #define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) +/* secondary interrupt of INT #9 */ +#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2) +#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0) +#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1) +#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2) + /* secondary interrupt of INT #17 */ -#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2) +#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3) #define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) #define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) #define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) @@ -212,11 +218,16 @@ #define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) /* secondary interrupt of INT #51 */ -#define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15) -#define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0) -#define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1) +#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15) +#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0) +#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1) + +/* secondary interrupt of INT #55 */ +#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2) +#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0) +#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1) -#define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2) +#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2) #define IRQ_GPIO_START 128 #define MMP_NR_BUILTIN_GPIO 192 diff --git a/arch/arm/mach-mmp/include/mach/pm-mmp2.h b/arch/arm/mach-mmp/include/mach/pm-mmp2.h new file mode 100644 index 000000000000..98bd66ce8006 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pm-mmp2.h @@ -0,0 +1,61 @@ +/* + * MMP2 Power Management Routines + * + * This software program is licensed subject to the GNU General Public License + * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html + * + * (C) Copyright 2010 Marvell International Ltd. + * All Rights Reserved + */ + +#ifndef __MMP2_PM_H__ +#define __MMP2_PM_H__ + +#include <mach/addr-map.h> + +#define APMU_PJ_IDLE_CFG APMU_REG(0x018) +#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) +#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) +#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) +#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) +#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) + +#define APMU_SRAM_PWR_DWN APMU_REG(0x08c) + +#define MPMU_SCCR MPMU_REG(0x038) +#define MPMU_PCR_PJ MPMU_REG(0x1000) +#define MPMU_PCR_PJ_AXISD (1 << 31) +#define MPMU_PCR_PJ_SLPEN (1 << 29) +#define MPMU_PCR_PJ_SPSD (1 << 28) +#define MPMU_PCR_PJ_DDRCORSD (1 << 27) +#define MPMU_PCR_PJ_APBSD (1 << 26) +#define MPMU_PCR_PJ_INTCLR (1 << 24) +#define MPMU_PCR_PJ_SLPWP0 (1 << 23) +#define MPMU_PCR_PJ_SLPWP1 (1 << 22) +#define MPMU_PCR_PJ_SLPWP2 (1 << 21) +#define MPMU_PCR_PJ_SLPWP3 (1 << 20) +#define MPMU_PCR_PJ_VCTCXOSD (1 << 19) +#define MPMU_PCR_PJ_SLPWP4 (1 << 18) +#define MPMU_PCR_PJ_SLPWP5 (1 << 17) +#define MPMU_PCR_PJ_SLPWP6 (1 << 16) +#define MPMU_PCR_PJ_SLPWP7 (1 << 15) + +#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) +#define MPMU_CGR_PJ MPMU_REG(0x1024) +#define MPMU_WUCRM_PJ MPMU_REG(0x104c) +#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) +#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) + +enum { + POWER_MODE_ACTIVE = 0, + POWER_MODE_CORE_INTIDLE, + POWER_MODE_CORE_EXTIDLE, + POWER_MODE_APPS_IDLE, + POWER_MODE_APPS_SLEEP, + POWER_MODE_CHIP_SLEEP, + POWER_MODE_SYS_SLEEP, +}; + +extern void mmp2_pm_enter_lowpower_mode(int state); +extern int mmp2_set_wake(struct irq_data *d, unsigned int on); +#endif diff --git a/arch/arm/mach-mmp/include/mach/pm-pxa910.h b/arch/arm/mach-mmp/include/mach/pm-pxa910.h new file mode 100644 index 000000000000..8cac8ab5253d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pm-pxa910.h @@ -0,0 +1,77 @@ +/* + * PXA910 Power Management Routines + * + * This software program is licensed subject to the GNU General Public License + * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html + * + * (C) Copyright 2009 Marvell International Ltd. + * All Rights Reserved + */ + +#ifndef __PXA910_PM_H__ +#define __PXA910_PM_H__ + +#define APMU_MOH_IDLE_CFG APMU_REG(0x0018) +#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1) +#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5) +#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6) +#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16) +#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18) +#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21) +#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20) + +#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c) +#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0) + +#define MPMU_FCCR MPMU_REG(0x0008) +#define MPMU_APCR MPMU_REG(0x1000) +#define MPMU_APCR_AXISD (1 << 31) +#define MPMU_APCR_DSPSD (1 << 30) +#define MPMU_APCR_SLPEN (1 << 29) +#define MPMU_APCR_DTCMSD (1 << 28) +#define MPMU_APCR_DDRCORSD (1 << 27) +#define MPMU_APCR_APBSD (1 << 26) +#define MPMU_APCR_BBSD (1 << 25) +#define MPMU_APCR_SLPWP0 (1 << 23) +#define MPMU_APCR_SLPWP1 (1 << 22) +#define MPMU_APCR_SLPWP2 (1 << 21) +#define MPMU_APCR_SLPWP3 (1 << 20) +#define MPMU_APCR_VCTCXOSD (1 << 19) +#define MPMU_APCR_SLPWP4 (1 << 18) +#define MPMU_APCR_SLPWP5 (1 << 17) +#define MPMU_APCR_SLPWP6 (1 << 16) +#define MPMU_APCR_SLPWP7 (1 << 15) +#define MPMU_APCR_MSASLPEN (1 << 14) +#define MPMU_APCR_STBYEN (1 << 13) + +#define MPMU_AWUCRM MPMU_REG(0x104c) +#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25) +#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24) +#define MPMU_AWUCRM_SDH1 (1 << 23) +#define MPMU_AWUCRM_SDH2 (1 << 22) +#define MPMU_AWUCRM_KEYPRESS (1 << 21) +#define MPMU_AWUCRM_TRACKBALL (1 << 20) +#define MPMU_AWUCRM_NEWROTARY (1 << 19) +#define MPMU_AWUCRM_RTC_ALARM (1 << 17) +#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13) +#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12) +#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11) +#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10) +#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9) +#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8) +#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7)) + +enum { + POWER_MODE_ACTIVE = 0, + POWER_MODE_CORE_INTIDLE, + POWER_MODE_CORE_EXTIDLE, + POWER_MODE_APPS_IDLE, + POWER_MODE_APPS_SLEEP, + POWER_MODE_SYS_SLEEP, + POWER_MODE_HIBERNATE, + POWER_MODE_UDR, +}; + +extern int pxa910_set_wake(struct irq_data *data, unsigned int on); + +#endif diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index dc03d580a06d..09dcd6e2b6a8 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -16,6 +16,7 @@ extern void pxa168_clear_keypad_wakeup(void); #include <plat/pxa27x_keypad.h> #include <mach/cputype.h> #include <linux/pxa168_eth.h> +#include <linux/platform_data/mv_usb.h> extern struct pxa_device_desc pxa168_device_uart1; extern struct pxa_device_desc pxa168_device_uart2; @@ -36,12 +37,9 @@ extern struct pxa_device_desc pxa168_device_fb; extern struct pxa_device_desc pxa168_device_keypad; extern struct pxa_device_desc pxa168_device_eth; -struct pxa168_usb_pdata { - /* If NULL, default phy init routine for PXA168 would be called */ - int (*phy_init)(void __iomem *usb_phy_reg_base); -}; /* pdata can be NULL */ -int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata); +extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata); + extern struct platform_device pxa168_device_gpio; diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index e2e1f1e5e124..793634c837ef 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -20,6 +20,9 @@ extern struct pxa_device_desc pxa910_device_pwm2; extern struct pxa_device_desc pxa910_device_pwm3; extern struct pxa_device_desc pxa910_device_pwm4; extern struct pxa_device_desc pxa910_device_nand; +extern struct platform_device pxa168_device_u2o; +extern struct platform_device pxa168_device_u2ootg; +extern struct platform_device pxa168_device_u2oehci; extern struct platform_device pxa910_device_gpio; extern struct platform_device pxa910_device_rtc; diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 8a37fb003655..68b0c93ec6a1 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -13,9 +13,6 @@ #include <mach/addr-map.h> -#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) -#define APBC_REG(x) (APBC_VIRT_BASE + (x)) - /* * APB clock register offsets for PXA168 */ diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h index 8447ac63e28f..7af8deb63e83 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h @@ -13,9 +13,6 @@ #include <mach/addr-map.h> -#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) -#define APMU_REG(x) (APMU_VIRT_BASE + (x)) - /* Clock Reset Control */ #define APMU_IRE APMU_REG(0x048) #define APMU_LCD APMU_REG(0x04c) diff --git a/arch/arm/mach-mmp/include/mach/regs-usb.h b/arch/arm/mach-mmp/include/mach/regs-usb.h new file mode 100644 index 000000000000..b047bf487506 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-usb.h @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2011 Marvell International Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_ARCH_REGS_USB_H +#define __ASM_ARCH_REGS_USB_H + +#define PXA168_U2O_REGBASE (0xd4208000) +#define PXA168_U2O_PHYBASE (0xd4207000) + +#define PXA168_U2H_REGBASE (0xd4209000) +#define PXA168_U2H_PHYBASE (0xd4206000) + +#define MMP3_HSIC1_REGBASE (0xf0001000) +#define MMP3_HSIC1_PHYBASE (0xf0001800) + +#define MMP3_HSIC2_REGBASE (0xf0002000) +#define MMP3_HSIC2_PHYBASE (0xf0002800) + +#define MMP3_FSIC_REGBASE (0xf0003000) +#define MMP3_FSIC_PHYBASE (0xf0003800) + + +#define USB_REG_RANGE (0x1ff) +#define USB_PHY_RANGE (0xff) + +/* registers */ +#define U2x_CAPREGS_OFFSET 0x100 + +/* phy regs */ +#define UTMI_REVISION 0x0 +#define UTMI_CTRL 0x4 +#define UTMI_PLL 0x8 +#define UTMI_TX 0xc +#define UTMI_RX 0x10 +#define UTMI_IVREF 0x14 +#define UTMI_T0 0x18 +#define UTMI_T1 0x1c +#define UTMI_T2 0x20 +#define UTMI_T3 0x24 +#define UTMI_T4 0x28 +#define UTMI_T5 0x2c +#define UTMI_RESERVE 0x30 +#define UTMI_USB_INT 0x34 +#define UTMI_DBG_CTL 0x38 +#define UTMI_OTG_ADDON 0x3c + +/* For UTMICTRL Register */ +#define UTMI_CTRL_USB_CLK_EN (1 << 31) +/* pxa168 */ +#define UTMI_CTRL_SUSPEND_SET1 (1 << 30) +#define UTMI_CTRL_SUSPEND_SET2 (1 << 29) +#define UTMI_CTRL_RXBUF_PDWN (1 << 24) +#define UTMI_CTRL_TXBUF_PDWN (1 << 11) + +#define UTMI_CTRL_INPKT_DELAY_SHIFT 30 +#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28 +#define UTMI_CTRL_PU_REF_SHIFT 20 +#define UTMI_CTRL_ARC_PULLDN_SHIFT 12 +#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1 +#define UTMI_CTRL_PWR_UP_SHIFT 0 + +/* For UTMI_PLL Register */ +#define UTMI_PLL_PLLCALI12_SHIFT 29 +#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29) + +#define UTMI_PLL_PLLVDD18_SHIFT 27 +#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27) + +#define UTMI_PLL_PLLVDD12_SHIFT 25 +#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25) + +#define UTMI_PLL_CLK_BLK_EN_SHIFT 24 +#define CLK_BLK_EN (0x1 << 24) +#define PLL_READY (0x1 << 23) +#define KVCO_EXT (0x1 << 22) +#define VCOCAL_START (0x1 << 21) + +#define UTMI_PLL_KVCO_SHIFT 15 +#define UTMI_PLL_KVCO_MASK (0x7 << 15) + +#define UTMI_PLL_ICP_SHIFT 12 +#define UTMI_PLL_ICP_MASK (0x7 << 12) + +#define UTMI_PLL_FBDIV_SHIFT 4 +#define UTMI_PLL_FBDIV_MASK (0xFF << 4) + +#define UTMI_PLL_REFDIV_SHIFT 0 +#define UTMI_PLL_REFDIV_MASK (0xF << 0) + +/* For UTMI_TX Register */ +#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27 +#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27) + +#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26 +#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26) + +#define UTMI_TX_TXVDD12_SHIFT 22 +#define UTMI_TX_TXVDD12_MASK (0x3 << 22) + +#define UTMI_TX_CK60_PHSEL_SHIFT 17 +#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17) + +#define UTMI_TX_IMPCAL_VTH_SHIFT 14 +#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14) + +#define REG_RCAL_START (0x1 << 12) + +#define UTMI_TX_LOW_VDD_EN_SHIFT 11 + +#define UTMI_TX_AMP_SHIFT 0 +#define UTMI_TX_AMP_MASK (0x7 << 0) + +/* For UTMI_RX Register */ +#define UTMI_REG_SQ_LENGTH_SHIFT 15 +#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15) + +#define UTMI_RX_SQ_THRESH_SHIFT 4 +#define UTMI_RX_SQ_THRESH_MASK (0xf << 4) + +#define UTMI_OTG_ADDON_OTG_ON (1 << 0) + +/* For MMP3 USB Phy */ +#define USB2_PLL_REG0 0x4 +#define USB2_PLL_REG1 0x8 +#define USB2_TX_REG0 0x10 +#define USB2_TX_REG1 0x14 +#define USB2_TX_REG2 0x18 +#define USB2_RX_REG0 0x20 +#define USB2_RX_REG1 0x24 +#define USB2_RX_REG2 0x28 +#define USB2_ANA_REG0 0x30 +#define USB2_ANA_REG1 0x34 +#define USB2_ANA_REG2 0x38 +#define USB2_DIG_REG0 0x3C +#define USB2_DIG_REG1 0x40 +#define USB2_DIG_REG2 0x44 +#define USB2_DIG_REG3 0x48 +#define USB2_TEST_REG0 0x4C +#define USB2_TEST_REG1 0x50 +#define USB2_TEST_REG2 0x54 +#define USB2_CHARGER_REG0 0x58 +#define USB2_OTG_REG0 0x5C +#define USB2_PHY_MON0 0x60 +#define USB2_RESETVE_REG0 0x64 +#define USB2_ICID_REG0 0x78 +#define USB2_ICID_REG1 0x7C + +/* USB2_PLL_REG0 */ +/* This is for Ax stepping */ +#define USB2_PLL_FBDIV_SHIFT_MMP3 0 +#define USB2_PLL_FBDIV_MASK_MMP3 (0xFF << 0) + +#define USB2_PLL_REFDIV_SHIFT_MMP3 8 +#define USB2_PLL_REFDIV_MASK_MMP3 (0xF << 8) + +#define USB2_PLL_VDD12_SHIFT_MMP3 12 +#define USB2_PLL_VDD18_SHIFT_MMP3 14 + +/* This is for B0 stepping */ +#define USB2_PLL_FBDIV_SHIFT_MMP3_B0 0 +#define USB2_PLL_REFDIV_SHIFT_MMP3_B0 9 +#define USB2_PLL_VDD18_SHIFT_MMP3_B0 14 +#define USB2_PLL_FBDIV_MASK_MMP3_B0 0x01FF +#define USB2_PLL_REFDIV_MASK_MMP3_B0 0x3E00 + +#define USB2_PLL_CAL12_SHIFT_MMP3 0 +#define USB2_PLL_CALI12_MASK_MMP3 (0x3 << 0) + +#define USB2_PLL_VCOCAL_START_SHIFT_MMP3 2 + +#define USB2_PLL_KVCO_SHIFT_MMP3 4 +#define USB2_PLL_KVCO_MASK_MMP3 (0x7<<4) + +#define USB2_PLL_ICP_SHIFT_MMP3 8 +#define USB2_PLL_ICP_MASK_MMP3 (0x7<<8) + +#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3 12 + +#define USB2_PLL_PU_PLL_SHIFT_MMP3 13 +#define USB2_PLL_PU_PLL_MASK (0x1 << 13) + +#define USB2_PLL_READY_MASK_MMP3 (0x1 << 15) + +/* USB2_TX_REG0 */ +#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3 8 +#define USB2_TX_IMPCAL_VTH_MASK_MMP3 (0x7 << 8) + +#define USB2_TX_RCAL_START_SHIFT_MMP3 13 + +/* USB2_TX_REG1 */ +#define USB2_TX_CK60_PHSEL_SHIFT_MMP3 0 +#define USB2_TX_CK60_PHSEL_MASK_MMP3 (0xf << 0) + +#define USB2_TX_AMP_SHIFT_MMP3 4 +#define USB2_TX_AMP_MASK_MMP3 (0x7 << 4) + +#define USB2_TX_VDD12_SHIFT_MMP3 8 +#define USB2_TX_VDD12_MASK_MMP3 (0x3 << 8) + +/* USB2_TX_REG2 */ +#define USB2_TX_DRV_SLEWRATE_SHIFT 10 + +/* USB2_RX_REG0 */ +#define USB2_RX_SQ_THRESH_SHIFT_MMP3 4 +#define USB2_RX_SQ_THRESH_MASK_MMP3 (0xf << 4) + +#define USB2_RX_SQ_LENGTH_SHIFT_MMP3 10 +#define USB2_RX_SQ_LENGTH_MASK_MMP3 (0x3 << 10) + +/* USB2_ANA_REG1*/ +#define USB2_ANA_PU_ANA_SHIFT_MMP3 14 + +/* USB2_OTG_REG0 */ +#define USB2_OTG_PU_OTG_SHIFT_MMP3 3 + +/* fsic registers */ +#define FSIC_MISC 0x4 +#define FSIC_INT 0x28 +#define FSIC_CTRL 0x30 + +/* HSIC registers */ +#define HSIC_PAD_CTRL 0x4 + +#define HSIC_CTRL 0x8 +#define HSIC_CTRL_HSIC_ENABLE (1<<7) +#define HSIC_CTRL_PLL_BYPASS (1<<4) + +#define TEST_GRP_0 0xc +#define TEST_GRP_1 0x10 + +#define HSIC_INT 0x14 +#define HSIC_INT_READY_INT_EN (1<<10) +#define HSIC_INT_CONNECT_INT_EN (1<<9) +#define HSIC_INT_CORE_INT_EN (1<<8) +#define HSIC_INT_HS_READY (1<<2) +#define HSIC_INT_CONNECT (1<<1) +#define HSIC_INT_CORE (1<<0) + +#define HSIC_CONFIG 0x18 +#define USBHSIC_CTRL 0x20 + +#define HSIC_USB_CTRL 0x28 +#define HSIC_USB_CTRL_CLKEN 1 +#define HSIC_USB_CLK_PHY 0x0 +#define HSIC_USB_CLK_PMU 0x1 + +#endif /* __ASM_ARCH_PXA_U2O_H */ |
