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-rw-r--r--arch/arm/mach-imx/gpc.c217
-rw-r--r--arch/arm/mach-imx/mach-imx25.c6
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c7
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c4
-rw-r--r--arch/arm/mach-imx/mach-pcm037_eet.c4
-rw-r--r--arch/arm/mach-imx/mmdc.c20
6 files changed, 34 insertions, 224 deletions
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 1dc2a34b9dbd..93f584ba0130 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -10,26 +10,17 @@
* http://www.gnu.org/copyleft/gpl.html
*/
-#include <linux/clk.h>
-#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <linux/pm_domain.h>
-#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
#include "hardware.h"
-#define GPC_CNTR 0x000
#define GPC_IMR1 0x008
-#define GPC_PGC_GPU_PDN 0x260
-#define GPC_PGC_GPU_PUPSCR 0x264
-#define GPC_PGC_GPU_PDNSCR 0x268
#define GPC_PGC_CPU_PDN 0x2a0
#define GPC_PGC_CPU_PUPSCR 0x2a4
#define GPC_PGC_CPU_PDNSCR 0x2a8
@@ -39,18 +30,6 @@
#define IMR_NUM 4
#define GPC_MAX_IRQS (IMR_NUM * 32)
-#define GPU_VPU_PUP_REQ BIT(1)
-#define GPU_VPU_PDN_REQ BIT(0)
-
-#define GPC_CLK_MAX 6
-
-struct pu_domain {
- struct generic_pm_domain base;
- struct regulator *reg;
- struct clk *clk[GPC_CLK_MAX];
- int num_clks;
-};
-
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
@@ -296,199 +275,3 @@ void __init imx_gpc_check_dt(void)
gpc_base = of_iomap(np, 0);
}
}
-
-static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
-{
- int iso, iso2sw;
- u32 val;
-
- /* Read ISO and ISO2SW power down delays */
- val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
- iso = val & 0x3f;
- iso2sw = (val >> 8) & 0x3f;
-
- /* Gate off PU domain when GPU/VPU when powered down */
- writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
-
- /* Request GPC to power down GPU/VPU */
- val = readl_relaxed(gpc_base + GPC_CNTR);
- val |= GPU_VPU_PDN_REQ;
- writel_relaxed(val, gpc_base + GPC_CNTR);
-
- /* Wait ISO + ISO2SW IPG clock cycles */
- ndelay((iso + iso2sw) * 1000 / 66);
-}
-
-static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
-{
- struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
-
- _imx6q_pm_pu_power_off(genpd);
-
- if (pu->reg)
- regulator_disable(pu->reg);
-
- return 0;
-}
-
-static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
-{
- struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
- int i, ret, sw, sw2iso;
- u32 val;
-
- if (pu->reg)
- ret = regulator_enable(pu->reg);
- if (pu->reg && ret) {
- pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
- return ret;
- }
-
- /* Enable reset clocks for all devices in the PU domain */
- for (i = 0; i < pu->num_clks; i++)
- clk_prepare_enable(pu->clk[i]);
-
- /* Gate off PU domain when GPU/VPU when powered down */
- writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
-
- /* Read ISO and ISO2SW power down delays */
- val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
- sw = val & 0x3f;
- sw2iso = (val >> 8) & 0x3f;
-
- /* Request GPC to power up GPU/VPU */
- val = readl_relaxed(gpc_base + GPC_CNTR);
- val |= GPU_VPU_PUP_REQ;
- writel_relaxed(val, gpc_base + GPC_CNTR);
-
- /* Wait ISO + ISO2SW IPG clock cycles */
- ndelay((sw + sw2iso) * 1000 / 66);
-
- /* Disable reset clocks for all devices in the PU domain */
- for (i = 0; i < pu->num_clks; i++)
- clk_disable_unprepare(pu->clk[i]);
-
- return 0;
-}
-
-static struct generic_pm_domain imx6q_arm_domain = {
- .name = "ARM",
-};
-
-static struct pu_domain imx6q_pu_domain = {
- .base = {
- .name = "PU",
- .power_off = imx6q_pm_pu_power_off,
- .power_on = imx6q_pm_pu_power_on,
- },
-};
-
-static struct generic_pm_domain imx6sl_display_domain = {
- .name = "DISPLAY",
-};
-
-static struct generic_pm_domain *imx_gpc_domains[] = {
- &imx6q_arm_domain,
- &imx6q_pu_domain.base,
- &imx6sl_display_domain,
-};
-
-static struct genpd_onecell_data imx_gpc_onecell_data = {
- .domains = imx_gpc_domains,
- .num_domains = ARRAY_SIZE(imx_gpc_domains),
-};
-
-static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
-{
- struct clk *clk;
- int i, ret;
-
- imx6q_pu_domain.reg = pu_reg;
-
- for (i = 0; ; i++) {
- clk = of_clk_get(dev->of_node, i);
- if (IS_ERR(clk))
- break;
- if (i >= GPC_CLK_MAX) {
- dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
- goto clk_err;
- }
- imx6q_pu_domain.clk[i] = clk;
- }
- imx6q_pu_domain.num_clks = i;
-
- /* Enable power always in case bootloader disabled it. */
- imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
-
- if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
- return 0;
-
- imx6q_pu_domain.base.states = devm_kzalloc(dev,
- sizeof(*imx6q_pu_domain.base.states),
- GFP_KERNEL);
- if (!imx6q_pu_domain.base.states)
- return -ENOMEM;
-
- imx6q_pu_domain.base.states[0].power_off_latency_ns = 25000;
- imx6q_pu_domain.base.states[0].power_on_latency_ns = 2000000;
- imx6q_pu_domain.base.state_count = 1;
-
- for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
- pm_genpd_init(imx_gpc_domains[i], NULL, false);
-
- ret = of_genpd_add_provider_onecell(dev->of_node,
- &imx_gpc_onecell_data);
- if (ret)
- goto power_off;
-
- return 0;
-
-power_off:
- imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
-clk_err:
- while (i--)
- clk_put(imx6q_pu_domain.clk[i]);
- imx6q_pu_domain.reg = NULL;
- return -EINVAL;
-}
-
-static int imx_gpc_probe(struct platform_device *pdev)
-{
- struct regulator *pu_reg;
- int ret;
-
- /* bail out if DT too old and doesn't provide the necessary info */
- if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
- return 0;
-
- pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
- if (PTR_ERR(pu_reg) == -ENODEV)
- pu_reg = NULL;
- if (IS_ERR(pu_reg)) {
- ret = PTR_ERR(pu_reg);
- dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
- return ret;
- }
-
- return imx_gpc_genpd_init(&pdev->dev, pu_reg);
-}
-
-static const struct of_device_id imx_gpc_dt_ids[] = {
- { .compatible = "fsl,imx6q-gpc" },
- { .compatible = "fsl,imx6sl-gpc" },
- { }
-};
-
-static struct platform_driver imx_gpc_driver = {
- .driver = {
- .name = "imx-gpc",
- .of_match_table = imx_gpc_dt_ids,
- },
- .probe = imx_gpc_probe,
-};
-
-static int __init imx_pgc_init(void)
-{
- return platform_driver_register(&imx_gpc_driver);
-}
-subsys_initcall(imx_pgc_init);
diff --git a/arch/arm/mach-imx/mach-imx25.c b/arch/arm/mach-imx/mach-imx25.c
index 32dcb5e99e23..353b86e3808f 100644
--- a/arch/arm/mach-imx/mach-imx25.c
+++ b/arch/arm/mach-imx/mach-imx25.c
@@ -23,6 +23,11 @@ static void __init imx25_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX25);
}
+static void __init imx25_dt_init(void)
+{
+ imx_aips_allow_unprivileged_access("fsl,imx25-aips");
+}
+
static void __init mx25_init_irq(void)
{
struct device_node *np;
@@ -41,6 +46,7 @@ static const char * const imx25_dt_board_compat[] __initconst = {
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
.init_early = imx25_init_early,
+ .init_machine = imx25_dt_init,
.init_late = imx25_pm_init,
.init_irq = mx25_init_irq,
.dt_compat = imx25_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 558e5f8589cb..68c3f0799d5b 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -375,6 +375,8 @@ static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = {
/* SPI */
static int spi0_internal_chipselect[] = {
+ MXC_SPI_CS(0),
+ MXC_SPI_CS(1),
MXC_SPI_CS(2),
};
@@ -385,6 +387,7 @@ static const struct spi_imx_master spi0_pdata __initconst = {
static int spi1_internal_chipselect[] = {
MXC_SPI_CS(0),
+ MXC_SPI_CS(1),
MXC_SPI_CS(2),
};
@@ -398,7 +401,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
.modalias = "mc13783",
.max_speed_hz = 1000000,
.bus_num = 1,
- .chip_select = 1, /* SS2 */
+ .chip_select = 2, /* SS2 */
.platform_data = &mc13783_pdata,
/* irq number is run-time assigned */
.mode = SPI_CS_HIGH,
@@ -406,7 +409,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
.modalias = "l4f00242t03",
.max_speed_hz = 5000000,
.bus_num = 0,
- .chip_select = 0, /* SS2 */
+ .chip_select = 2, /* SS2 */
.platform_data = &mx31_3ds_l4f00242t03_pdata,
},
};
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index cc867682520e..bde9a9af6714 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -296,14 +296,14 @@ static struct spi_board_info moboard_spi_board_info[] __initdata = {
/* irq number is run-time assigned */
.max_speed_hz = 300000,
.bus_num = 1,
- .chip_select = 0,
+ .chip_select = 1,
.platform_data = &moboard_pmic,
.mode = SPI_CS_HIGH,
},
};
static int moboard_spi2_cs[] = {
- MXC_SPI_CS(1),
+ MXC_SPI_CS(0), MXC_SPI_CS(1),
};
static const struct spi_imx_master moboard_spi2_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
index 8fd8255068ee..95bd97710494 100644
--- a/arch/arm/mach-imx/mach-pcm037_eet.c
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -50,13 +50,13 @@ static struct spi_board_info pcm037_spi_dev[] = {
.modalias = "dac124s085",
.max_speed_hz = 400000,
.bus_num = 0,
- .chip_select = 0, /* Index in pcm037_spi1_cs[] */
+ .chip_select = 1, /* Index in pcm037_spi1_cs[] */
.mode = SPI_CPHA,
},
};
/* Platform Data for MXC CSPI */
-static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
+static int pcm037_spi1_cs[] = { MXC_SPI_CS(0), MXC_SPI_CS(1), };
static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
.chipselect = pcm037_spi1_cs,
diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c
index c03bf28d8bbc..78262899a590 100644
--- a/arch/arm/mach-imx/mmdc.c
+++ b/arch/arm/mach-imx/mmdc.c
@@ -1,4 +1,5 @@
/*
+ * Copyright 2017 NXP
* Copyright 2011,2016 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
@@ -47,6 +48,7 @@
#define PROFILE_SEL 0x10
#define MMDC_MADPCR0 0x410
+#define MMDC_MADPCR1 0x414
#define MMDC_MADPSR0 0x418
#define MMDC_MADPSR1 0x41C
#define MMDC_MADPSR2 0x420
@@ -57,6 +59,7 @@
#define MMDC_NUM_COUNTERS 6
#define MMDC_FLAG_PROFILE_SEL 0x1
+#define MMDC_PRF_AXI_ID_CLEAR 0x0
#define to_mmdc_pmu(p) container_of(p, struct mmdc_pmu, pmu)
@@ -87,7 +90,7 @@ static DEFINE_IDA(mmdc_ida);
PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
-PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "config=0x03")
+PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
@@ -161,8 +164,11 @@ static struct attribute_group mmdc_pmu_events_attr_group = {
};
PMU_FORMAT_ATTR(event, "config:0-63");
+PMU_FORMAT_ATTR(axi_id, "config1:0-63");
+
static struct attribute *mmdc_pmu_format_attrs[] = {
&format_attr_event.attr,
+ &format_attr_axi_id.attr,
NULL,
};
@@ -345,6 +351,14 @@ static void mmdc_pmu_event_start(struct perf_event *event, int flags)
writel(DBG_RST, reg);
+ /*
+ * Write the AXI id parameter to MADPCR1.
+ */
+ val = event->attr.config1;
+ reg = mmdc_base + MMDC_MADPCR1;
+ writel(val, reg);
+
+ reg = mmdc_base + MMDC_MADPCR0;
val = DBG_EN;
if (pmu_mmdc->devtype_data->flags & MMDC_FLAG_PROFILE_SEL)
val |= PROFILE_SEL;
@@ -382,6 +396,10 @@ static void mmdc_pmu_event_stop(struct perf_event *event, int flags)
reg = mmdc_base + MMDC_MADPCR0;
writel(PRF_FRZ, reg);
+
+ reg = mmdc_base + MMDC_MADPCR1;
+ writel(MMDC_PRF_AXI_ID_CLEAR, reg);
+
mmdc_pmu_event_update(event);
}
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