diff options
Diffstat (limited to 'arch/arm/mach-highbank/sysregs.h')
-rw-r--r-- | arch/arm/mach-highbank/sysregs.h | 42 |
1 files changed, 38 insertions, 4 deletions
diff --git a/arch/arm/mach-highbank/sysregs.h b/arch/arm/mach-highbank/sysregs.h index 0e913389f445..70af9d13fcef 100644 --- a/arch/arm/mach-highbank/sysregs.h +++ b/arch/arm/mach-highbank/sysregs.h @@ -17,6 +17,10 @@ #define _MACH_HIGHBANK__SYSREGS_H_ #include <linux/io.h> +#include <linux/smp.h> +#include <asm/smp_plat.h> +#include <asm/smp_scu.h> +#include "core.h" extern void __iomem *sregs_base; @@ -29,24 +33,54 @@ extern void __iomem *sregs_base; #define HB_PWR_HARD_RESET 2 #define HB_PWR_SHUTDOWN 3 -static inline void hignbank_set_pwr_suspend(void) +#define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4)) + +static inline void highbank_set_core_pwr(void) +{ + int cpu = cpu_logical_map(smp_processor_id()); + if (scu_base_addr) + scu_power_mode(scu_base_addr, SCU_PM_POWEROFF); + else + writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu)); +} + +static inline void highbank_clear_core_pwr(void) +{ + int cpu = cpu_logical_map(smp_processor_id()); + if (scu_base_addr) + scu_power_mode(scu_base_addr, SCU_PM_NORMAL); + else + writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu)); +} + +static inline void highbank_set_pwr_suspend(void) { writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); + highbank_set_core_pwr(); } -static inline void hignbank_set_pwr_shutdown(void) +static inline void highbank_set_pwr_shutdown(void) { writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); + highbank_set_core_pwr(); } -static inline void hignbank_set_pwr_soft_reset(void) +static inline void highbank_set_pwr_soft_reset(void) { writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); + highbank_set_core_pwr(); } -static inline void hignbank_set_pwr_hard_reset(void) +static inline void highbank_set_pwr_hard_reset(void) { writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); + highbank_set_core_pwr(); +} + +static inline void highbank_clear_pwr_request(void) +{ + writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); + highbank_clear_core_pwr(); } #endif |