diff options
| -rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 4 | ||||
| -rw-r--r-- | include/linux/stmmac.h | 33 |
2 files changed, 19 insertions, 18 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c index 83292f4edc6b..1a420142f6ac 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c @@ -70,7 +70,7 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) int data; u16 regValue = (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))); - regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); + regValue |= MII_BUSY | ((priv->plat->clk_csr & 0xF) << 2); if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) return -EBUSY; @@ -106,7 +106,7 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) | MII_WRITE; - value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2); + value |= MII_BUSY | ((priv->plat->clk_csr & 0xF) << 2); /* Wait until any existing MII operation is complete */ if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address)) diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 4aef9baff12b..cf6403186359 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -37,28 +37,29 @@ * This could also be configured at run time using CPU freq framework. */ /* MDC Clock Selection define*/ -#define STMMAC_CSR_60_100M 0 /* MDC = clk_scr_i/42 */ -#define STMMAC_CSR_100_150M 1 /* MDC = clk_scr_i/62 */ -#define STMMAC_CSR_20_35M 2 /* MDC = clk_scr_i/16 */ -#define STMMAC_CSR_35_60M 3 /* MDC = clk_scr_i/26 */ -#define STMMAC_CSR_150_250M 4 /* MDC = clk_scr_i/102 */ -#define STMMAC_CSR_250_300M 5 /* MDC = clk_scr_i/122 */ - -/* FIXME: The MDC clock could be set higher than the IEEE 802.3 +#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ +#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ +#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ +#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ +#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ +#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ + +/* The MDC clock could be set higher than the IEEE 802.3 * specified frequency limit 0f 2.5 MHz, by programming a clock divider * of value different than the above defined values. The resultant MDIO * clock frequency of 12.5 MHz is applicable for the interfacing chips * supporting higher MDC clocks. * The MDC clock selection macros need to be defined for MDC clock rate * of 12.5 MHz, corresponding to the following selection. - * 1000 clk_csr_i/4 - * 1001 clk_csr_i/6 - * 1010 clk_csr_i/8 - * 1011 clk_csr_i/10 - * 1100 clk_csr_i/12 - * 1101 clk_csr_i/14 - * 1110 clk_csr_i/16 - * 1111 clk_csr_i/18 */ + */ +#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ +#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ +#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ +#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ +#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ +#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ +#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ +#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ /* AXI DMA Burst length suported */ #define DMA_AXI_BLEN_4 (1 << 1) |
