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| author | Kyle McMartin <kyle@parisc-linux.org> | 2006-08-13 20:37:26 -0400 |
|---|---|---|
| committer | Matthew Wilcox <willy@parisc-linux.org> | 2006-10-04 06:44:58 -0600 |
| commit | 32104b29cdf93f78ac37e681bd4547413466d13c (patch) | |
| tree | 4b058cad9227dd960da79daf94235517690f9197 /include/asm-parisc | |
| parent | 4068d93cd17561bcbfc821c831cb048385320bd6 (diff) | |
| download | talos-op-linux-32104b29cdf93f78ac37e681bd4547413466d13c.tar.gz talos-op-linux-32104b29cdf93f78ac37e681bd4547413466d13c.zip | |
[PARISC] PA7200 also supports prefetch for read
It seems PA7200 processors also suppress traps on loads to
%r0. This means we can prefetch for read on these cpus. Of course,
we can't support prefetch for write, since that requires
LOAD DOUBLEWORD which was added with PA2.0
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'include/asm-parisc')
| -rw-r--r-- | include/asm-parisc/prefetch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-parisc/prefetch.h b/include/asm-parisc/prefetch.h index f5a2e7ae2662..5d021726fa33 100644 --- a/include/asm-parisc/prefetch.h +++ b/include/asm-parisc/prefetch.h @@ -24,11 +24,14 @@ extern inline void prefetch(const void *addr) __asm__("ldw 0(%0), %%r0" : : "r" (addr)); } +/* LDD is a PA2.0 addition. */ +#ifdef CONFIG_PA20 #define ARCH_HAS_PREFETCHW extern inline void prefetchw(const void *addr) { __asm__("ldd 0(%0), %%r0" : : "r" (addr)); } +#endif /* CONFIG_PA20 */ #endif /* CONFIG_PREFETCH */ #endif /* __ASSEMBLY__ */ |
