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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-07-13 19:47:28 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:31:49 +0100 |
| commit | 7a0fc58cd9b004672b38537de276f8f188d5e84a (patch) | |
| tree | 68cc64c5bf4fc62e5aae4b38357125aaf6cc6cdd /include/asm-mips | |
| parent | 55d04dff0fcf5d1c3f0d6edf6df86d82fa4c053b (diff) | |
| download | talos-op-linux-7a0fc58cd9b004672b38537de276f8f188d5e84a.tar.gz talos-op-linux-7a0fc58cd9b004672b38537de276f8f188d5e84a.zip | |
A few more macros to access MIPS R2 architecture registers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
| -rw-r--r-- | include/asm-mips/mipsregs.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 2a56929df9c2..802b1c41ff6a 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -96,6 +96,16 @@ #define CP0_S1_INTCONTROL $20 /* + * Coprocessor 0 Set 2 register names + */ +#define CP0_S2_SRSCTL $12 /* MIPSR2 */ + +/* + * Coprocessor 0 Set 3 register names + */ +#define CP0_S3_SRSMAP $12 /* MIPSR2 */ + +/* * TX39 Series */ #define CP0_TX39_CACHE $7 @@ -984,6 +994,22 @@ do { \ #define read_c0_errorepc() __read_ulong_c0_register($30, 0) #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) +/* MIPSR2 */ +#define read_c0_hwrena() __read_32bit_c0_register($7,0) +#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) + +#define read_c0_intctl() __read_32bit_c0_register($12, 1) +#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) + +#define read_c0_srsctl() __read_32bit_c0_register($12, 2) +#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) + +#define read_c0_srsmap() __read_32bit_c0_register($12, 3) +#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) + +#define read_c0_ebase() __read_32bit_c0_register($15,1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) + /* * Macros to access the floating point coprocessor control registers */ @@ -1357,6 +1383,8 @@ __BUILD_SET_C0(status) __BUILD_SET_C0(cause) __BUILD_SET_C0(config) __BUILD_SET_C0(intcontrol) +__BUILD_SET_C0(intctl) +__BUILD_SET_C0(srsmap) #endif /* !__ASSEMBLY__ */ |
