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| author | Jesper Nilsson <jespern@stork.se.axis.com> | 2007-11-29 17:21:59 +0100 |
|---|---|---|
| committer | Jesper Nilsson <jesper.nilsson@axis.com> | 2008-02-08 11:06:23 +0100 |
| commit | 58d083192825c5fbd46fa0b1ff4d1ecc9118b692 (patch) | |
| tree | 3bd39bf385afe376272d4769c0af321d6e8ed992 /include/asm-cris/arch-v32/mach-a3/startup.inc | |
| parent | 035e111f9a9b29843bc899f03d56f19d94bebb53 (diff) | |
| download | talos-op-linux-58d083192825c5fbd46fa0b1ff4d1ecc9118b692.tar.gz talos-op-linux-58d083192825c5fbd46fa0b1ff4d1ecc9118b692.zip | |
CRIS v32: Add hardware dependent include files and defconfigs for ETRAX FS and ARTPEC-3 chips.
The header files describe the hardware registers available in both
these chips, note that most of this documentation is automatically
generated from the hardware implementation.
Diffstat (limited to 'include/asm-cris/arch-v32/mach-a3/startup.inc')
| -rw-r--r-- | include/asm-cris/arch-v32/mach-a3/startup.inc | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/include/asm-cris/arch-v32/mach-a3/startup.inc b/include/asm-cris/arch-v32/mach-a3/startup.inc new file mode 100644 index 000000000000..2f23e5e16f4a --- /dev/null +++ b/include/asm-cris/arch-v32/mach-a3/startup.inc @@ -0,0 +1,60 @@ +#include <hwregs/asm/reg_map_asm.h> +#include <hwregs/asm/gio_defs_asm.h> +#include <hwregs/asm/pio_defs_asm.h> +#include <hwregs/asm/clkgen_defs_asm.h> +#include <hwregs/asm/pinmux_defs_asm.h> + + .macro GIO_INIT + move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 + move.d $r0, [$r1] + + move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 + move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 + move.d $r0, [$r1] + + move.d 0xFFFFFFFF, $r0 + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1 + move.d $r0, [$r1] + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1 + move.d $r0, [$r1] + move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1 + move.d $r0, [$r1] + .endm + + .macro START_CLOCKS + move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1 + move.d [$r1], $r0 + or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \ + REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0 + move.d $r0, [$r1] + .endm + + .macro SETUP_WAIT_STATES + move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1 + move.d $r1, [$r0] + move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0 + move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1 + move.d $r1, [$r0] + .endm |
