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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-06-29 16:23:47 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-29 16:23:47 +0100 |
| commit | a144a5633c1e625c3134c2ce8d549a054468fd98 (patch) | |
| tree | 3dcb1d6821ee465bb804c786b59c6dabc5c61da1 /include/asm-arm/arch-omap/irqs.h | |
| parent | 8fc5ffa063f6551c9e6dd66cab89c46ad41e59c5 (diff) | |
| parent | 3cbc96050b02d8e5764bd0970067ef294737e324 (diff) | |
| download | talos-op-linux-a144a5633c1e625c3134c2ce8d549a054468fd98.tar.gz talos-op-linux-a144a5633c1e625c3134c2ce8d549a054468fd98.zip | |
Merge omap tree
* master.kernel.org:/pub/scm/linux/kernel/git/tmlind/linux-omap-upstream: (26 commits)
ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
ARM: OMAP: Update dmtimers
ARM: OMAP: Make clock variables static
ARM: OMAP: Fix GPMC compilation when DEBUG is defined
ARM: OMAP: Mux updates for external DMA and GPIO
ARM: OMAP: Add OMAP_TAG_CAMERA_SENSOR
ARM: OMAP: Add initial 24xx suspend support
ARM: OMAP: Update cpufreq support for 24xx
ARM: OMAP: Add GPMC support for OMAP2
ARM: OMAP: Fix DMA channel irq handling for omap24xx
ARM: OMAP: OMAP2 DMA burst support
ARM: OMAP: Fix 32 kHz timer and modify GP timer to use GPT1
ARM: OMAP: Port dmtimers to OMAP2 and implement PWM support
ARM: OMAP: Correct two bugs in arch/arm/mach-omap2/clock.c
ARM: OMAP: Register the 24xx McSPI device
ARM: OMAP: Add bitbank SPI driver for Innovator 1510 touchscreen
ARM: OMAP: Aic23 alsa platform driver code for board-innovator
ARM: OMAP: Fix GPIO IRQ mask handling
ARM: OMAP: DMA transfer parameter configuration fix
...
Diffstat (limited to 'include/asm-arm/arch-omap/irqs.h')
| -rw-r--r-- | include/asm-arm/arch-omap/irqs.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h index 42098d99f302..2542495d8a43 100644 --- a/include/asm-arm/arch-omap/irqs.h +++ b/include/asm-arm/arch-omap/irqs.h @@ -242,10 +242,24 @@ #define INT_24XX_GPIO_BANK2 30 #define INT_24XX_GPIO_BANK3 31 #define INT_24XX_GPIO_BANK4 32 +#define INT_24XX_GPTIMER1 37 +#define INT_24XX_GPTIMER2 38 +#define INT_24XX_GPTIMER3 39 +#define INT_24XX_GPTIMER4 40 +#define INT_24XX_GPTIMER5 41 +#define INT_24XX_GPTIMER6 42 +#define INT_24XX_GPTIMER7 43 +#define INT_24XX_GPTIMER8 44 +#define INT_24XX_GPTIMER9 45 +#define INT_24XX_GPTIMER10 46 +#define INT_24XX_GPTIMER11 47 +#define INT_24XX_GPTIMER12 48 #define INT_24XX_MCBSP1_IRQ_TX 59 #define INT_24XX_MCBSP1_IRQ_RX 60 #define INT_24XX_MCBSP2_IRQ_TX 62 #define INT_24XX_MCBSP2_IRQ_RX 63 +#define INT_24XX_UART1_IRQ 72 +#define INT_24XX_UART2_IRQ 73 #define INT_24XX_UART3_IRQ 74 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and |
