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authorAdam Jackson <ajax@redhat.com>2010-04-05 17:57:59 -0400
committerEric Anholt <eric@anholt.net>2010-04-12 09:23:47 -0700
commit9c9e792795f96d201d85188607261f9f8bbf3219 (patch)
treeabe0fb9928322bc0115b15da8b7584ef909525cb /drivers
parentab00a9ef8d4ce7de4d5b15cbf4101feeb8cf7f4d (diff)
downloadtalos-op-linux-9c9e792795f96d201d85188607261f9f8bbf3219.tar.gz
talos-op-linux-9c9e792795f96d201d85188607261f9f8bbf3219.zip
drm/i915: Set sync polarity correctly on DisplayPort
Probably only matters for format-converting dongles, but might as well get it right all the time. Signed-off-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fee54169493b..79625bd9361a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -638,9 +638,12 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dp_priv->DP = (DP_VOLTAGE_0_4 |
- DP_PRE_EMPHASIS_0 |
- DP_SYNC_VS_HIGH |
- DP_SYNC_HS_HIGH);
+ DP_PRE_EMPHASIS_0);
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ dp_priv->DP |= DP_SYNC_HS_HIGH;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ dp_priv->DP |= DP_SYNC_VS_HIGH;
if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
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