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authorPhilipp Zabel <philipp.zabel@gmail.com>2009-02-17 10:09:19 +0100
committerSamuel Ortiz <samuel@sortiz.org>2009-04-05 00:32:22 +0200
commit7d33ccbeecd8393cc690cf9a71008236cdd7cc2c (patch)
tree93b0356d89abf9ffa1c90da3a9b2e30b34074089 /drivers/w1/masters/ds1wm.c
parentb72019dbd126e60bb5f9f350f76127b1527facba (diff)
downloadtalos-op-linux-7d33ccbeecd8393cc690cf9a71008236cdd7cc2c.tar.gz
talos-op-linux-7d33ccbeecd8393cc690cf9a71008236cdd7cc2c.zip
mfd: remove DS1WM clock handling
This driver requests a clock that usually is supplied by the MFD in which the DS1WM is contained. Currently, it is impossible for a MFD to register their clocks with the generic clock API due to different implementations across architectures. For now, this patch removes the clock handling from DS1WM altogether, trusting that the MFD enable/disable functions will switch the clock if needed. The clock rate is obtained from a new parameter in driver_data. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Samuel Ortiz <sameo@openedhand.com>
Diffstat (limited to 'drivers/w1/masters/ds1wm.c')
-rw-r--r--drivers/w1/masters/ds1wm.c27
1 files changed, 7 insertions, 20 deletions
diff --git a/drivers/w1/masters/ds1wm.c b/drivers/w1/masters/ds1wm.c
index f1e6b3dd1e43..37f08c850608 100644
--- a/drivers/w1/masters/ds1wm.c
+++ b/drivers/w1/masters/ds1wm.c
@@ -16,7 +16,6 @@
#include <linux/irq.h>
#include <linux/pm.h>
#include <linux/platform_device.h>
-#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/mfd/core.h>
@@ -93,7 +92,6 @@ struct ds1wm_data {
struct mfd_cell *cell;
int irq;
int active_high;
- struct clk *clk;
int slave_present;
void *reset_complete;
void *read_complete;
@@ -216,17 +214,17 @@ static int ds1wm_find_divisor(int gclk)
static void ds1wm_up(struct ds1wm_data *ds1wm_data)
{
- int gclk, divisor;
+ int divisor;
+ struct ds1wm_driver_data *plat = ds1wm_data->cell->driver_data;
if (ds1wm_data->cell->enable)
ds1wm_data->cell->enable(ds1wm_data->pdev);
- gclk = clk_get_rate(ds1wm_data->clk);
- clk_enable(ds1wm_data->clk);
- divisor = ds1wm_find_divisor(gclk);
+ divisor = ds1wm_find_divisor(plat->clock_rate);
if (divisor == 0) {
dev_err(&ds1wm_data->pdev->dev,
- "no suitable divisor for %dHz clock\n", gclk);
+ "no suitable divisor for %dHz clock\n",
+ plat->clock_rate);
return;
}
ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
@@ -247,8 +245,6 @@ static void ds1wm_down(struct ds1wm_data *ds1wm_data)
if (ds1wm_data->cell->disable)
ds1wm_data->cell->disable(ds1wm_data->pdev);
-
- clk_disable(ds1wm_data->clk);
}
/* --------------------------------------------------------------------- */
@@ -385,26 +381,18 @@ static int ds1wm_probe(struct platform_device *pdev)
if (ret)
goto err1;
- ds1wm_data->clk = clk_get(&pdev->dev, "ds1wm");
- if (IS_ERR(ds1wm_data->clk)) {
- ret = PTR_ERR(ds1wm_data->clk);
- goto err2;
- }
-
ds1wm_up(ds1wm_data);
ds1wm_master.data = (void *)ds1wm_data;
ret = w1_add_master_device(&ds1wm_master);
if (ret)
- goto err3;
+ goto err2;
return 0;
-err3:
- ds1wm_down(ds1wm_data);
- clk_put(ds1wm_data->clk);
err2:
+ ds1wm_down(ds1wm_data);
free_irq(ds1wm_data->irq, ds1wm_data);
err1:
iounmap(ds1wm_data->map);
@@ -443,7 +431,6 @@ static int ds1wm_remove(struct platform_device *pdev)
w1_remove_master_device(&ds1wm_master);
ds1wm_down(ds1wm_data);
- clk_put(ds1wm_data->clk);
free_irq(ds1wm_data->irq, ds1wm_data);
iounmap(ds1wm_data->map);
kfree(ds1wm_data);
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