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author | Ingo Molnar <mingo@elte.hu> | 2010-05-03 09:17:01 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2010-05-03 09:17:01 +0200 |
commit | 53ba4f2fa73225113a488584df0d85d3cba52943 (patch) | |
tree | d85b984d9818abc3ccc0237eb53b710d9e96c39e /drivers/video/omap2/dss/dss.c | |
parent | bd6d29c25bb1a24a4c160ec5de43e0004e01f72b (diff) | |
parent | 66f41d4c5c8a5deed66fdcc84509376c9a0bf9d8 (diff) | |
download | talos-op-linux-53ba4f2fa73225113a488584df0d85d3cba52943.tar.gz talos-op-linux-53ba4f2fa73225113a488584df0d85d3cba52943.zip |
Merge commit 'v2.6.34-rc6' into core/locking
Diffstat (limited to 'drivers/video/omap2/dss/dss.c')
-rw-r--r-- | drivers/video/omap2/dss/dss.c | 45 |
1 files changed, 35 insertions, 10 deletions
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 0a26b7d84d41..54344184dd73 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -68,6 +68,9 @@ static struct { struct dss_clock_info cache_dss_cinfo; struct dispc_clock_info cache_dispc_cinfo; + enum dss_clk_source dsi_clk_source; + enum dss_clk_source dispc_clk_source; + u32 ctx[DSS_SZ_REGS / sizeof(u32)]; } dss; @@ -247,23 +250,42 @@ void dss_dump_regs(struct seq_file *s) #undef DUMPREG } -void dss_select_clk_source(bool dsi, bool dispc) +void dss_select_dispc_clk_source(enum dss_clk_source clk_src) { - u32 r; - r = dss_read_reg(DSS_CONTROL); - r = FLD_MOD(r, dsi, 1, 1); /* DSI_CLK_SWITCH */ - r = FLD_MOD(r, dispc, 0, 0); /* DISPC_CLK_SWITCH */ - dss_write_reg(DSS_CONTROL, r); + int b; + + BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && + clk_src != DSS_SRC_DSS1_ALWON_FCLK); + + b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; + + REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ + + dss.dispc_clk_source = clk_src; } -int dss_get_dsi_clk_source(void) +void dss_select_dsi_clk_source(enum dss_clk_source clk_src) { - return FLD_GET(dss_read_reg(DSS_CONTROL), 1, 1); + int b; + + BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && + clk_src != DSS_SRC_DSS1_ALWON_FCLK); + + b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; + + REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ + + dss.dsi_clk_source = clk_src; +} + +enum dss_clk_source dss_get_dispc_clk_source(void) +{ + return dss.dispc_clk_source; } -int dss_get_dispc_clk_source(void) +enum dss_clk_source dss_get_dsi_clk_source(void) { - return FLD_GET(dss_read_reg(DSS_CONTROL), 0, 0); + return dss.dsi_clk_source; } /* calculate clock rates using dividers in cinfo */ @@ -568,6 +590,9 @@ int dss_init(bool skip_init) } } + dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; + dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; + dss_save_context(); rev = dss_read_reg(DSS_REVISION); |