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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-11-17 07:53:25 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-11-17 07:53:25 -0800 |
commit | 847e9170c77d3b4f57822ae1f4cf4f65c65a8254 (patch) | |
tree | 23f931fa2c3f9cf967deb638fed9804806d07357 /drivers/net/niu.h | |
parent | 72eb8c6747b49e41fd2b042510f03ac7c13426fc (diff) | |
parent | 5f9021cfdc3524a4c5e3d7ae2d049eb7adcd6776 (diff) | |
download | talos-op-linux-847e9170c77d3b4f57822ae1f4cf4f65c65a8254.tar.gz talos-op-linux-847e9170c77d3b4f57822ae1f4cf4f65c65a8254.zip |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (27 commits)
rtnetlink: propagate error from dev_change_flags in do_setlink()
isdn: remove extra byteswap in isdn_net_ciscohdlck_slarp_send_reply
Phonet: refuse to send bigger than MTU packets
e1000e: fix IPMI traffic
e1000e: fix warn_on reload after phy_id error
phy: fix phy address bug
e100: fix dma error in direction for mapping
igb: use dev_printk instead of printk
qla3xxx: Cleanup: Fix link print statements.
igb: Use device_set_wakeup_enable
e1000: Use device_set_wakeup_enable
e1000e: Use device_set_wakeup_enable
via-velocity: enable perfect filtering for multicast packets
phy: Add support for Marvell 88E1118 PHY
mlx4_en: Pause parameters per port
phylib: fix premature freeing of struct mii_bus
atl1: Do not enumerate options unsupported by chip
atl1e: fix broken multicast by removing unnecessary crc inversion
gianfar: Fix DMA unmap invocations
net/ucc_geth: Fix oops in uec_get_ethtool_stats()
...
Diffstat (limited to 'drivers/net/niu.h')
-rw-r--r-- | drivers/net/niu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/niu.h b/drivers/net/niu.h index c6fa883daa22..180ca8ae93de 100644 --- a/drivers/net/niu.h +++ b/drivers/net/niu.h @@ -1048,6 +1048,13 @@ #define PLL_CFG_LD_SHIFT 8 #define PLL_CFG_MPY 0x0000001e #define PLL_CFG_MPY_SHIFT 1 +#define PLL_CFG_MPY_4X 0x0 +#define PLL_CFG_MPY_5X 0x00000002 +#define PLL_CFG_MPY_6X 0x00000004 +#define PLL_CFG_MPY_8X 0x00000008 +#define PLL_CFG_MPY_10X 0x0000000a +#define PLL_CFG_MPY_12X 0x0000000c +#define PLL_CFG_MPY_12P5X 0x0000000e #define PLL_CFG_ENPLL 0x00000001 #define ESR2_TI_PLL_STS_L (ESR2_BASE + 0x002) @@ -1093,6 +1100,9 @@ #define PLL_TX_CFG_INVPAIR 0x00000080 #define PLL_TX_CFG_RATE 0x00000060 #define PLL_TX_CFG_RATE_SHIFT 5 +#define PLL_TX_CFG_RATE_FULL 0x0 +#define PLL_TX_CFG_RATE_HALF 0x20 +#define PLL_TX_CFG_RATE_QUAD 0x40 #define PLL_TX_CFG_BUSWIDTH 0x0000001c #define PLL_TX_CFG_BUSWIDTH_SHIFT 2 #define PLL_TX_CFG_ENTEST 0x00000002 @@ -1132,6 +1142,9 @@ #define PLL_RX_CFG_INVPAIR 0x00000080 #define PLL_RX_CFG_RATE 0x00000060 #define PLL_RX_CFG_RATE_SHIFT 5 +#define PLL_RX_CFG_RATE_FULL 0x0 +#define PLL_RX_CFG_RATE_HALF 0x20 +#define PLL_RX_CFG_RATE_QUAD 0x40 #define PLL_RX_CFG_BUSWIDTH 0x0000001c #define PLL_RX_CFG_BUSWIDTH_SHIFT 2 #define PLL_RX_CFG_ENTEST 0x00000002 |