diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-07-08 12:22:38 +0100 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-07-08 10:23:06 -0700 |
| commit | f19a079a800dfd365fa8ed422acf29ca7a036ea3 (patch) | |
| tree | 90c8e7ffe4d8dcbd34887f8bcb352479f1936440 /drivers/gpu | |
| parent | 973d04f990ac241881c4793cdfbe367b3caf3dba (diff) | |
| download | talos-op-linux-f19a079a800dfd365fa8ed422acf29ca7a036ea3.tar.gz talos-op-linux-f19a079a800dfd365fa8ed422acf29ca7a036ea3.zip | |
drm/i915: Remove vestigial pitch from post-gen2 FBC control routines
The cfb_pitch was only used for 8xx_enable_fbc(), every later routine
was just overwriting the value with itself thanks to a copy'n'paste
error.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ab78dfd4dfb6..5c359e59d325 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1482,8 +1482,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) dpfc_ctl = I915_READ(DPFC_CONTROL); if (dpfc_ctl & DPFC_CTL_EN) { - if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && - dev_priv->cfb_fence == obj->fence_reg && + if (dev_priv->cfb_fence == obj->fence_reg && dev_priv->cfb_plane == intel_crtc->plane && dev_priv->cfb_y == crtc->y) return; @@ -1492,7 +1491,6 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) intel_wait_for_vblank(dev, intel_crtc->pipe); } - dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; dev_priv->cfb_fence = obj->fence_reg; dev_priv->cfb_plane = intel_crtc->plane; dev_priv->cfb_y = crtc->y; @@ -1572,8 +1570,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); if (dpfc_ctl & DPFC_CTL_EN) { - if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 && - dev_priv->cfb_fence == obj->fence_reg && + if (dev_priv->cfb_fence == obj->fence_reg && dev_priv->cfb_plane == intel_crtc->plane && dev_priv->cfb_offset == obj->gtt_offset && dev_priv->cfb_y == crtc->y) @@ -1583,7 +1580,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) intel_wait_for_vblank(dev, intel_crtc->pipe); } - dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1; dev_priv->cfb_fence = obj->fence_reg; dev_priv->cfb_plane = intel_crtc->plane; dev_priv->cfb_offset = obj->gtt_offset; |
