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| author | Akash Goel <akash.goel@intel.com> | 2014-11-25 12:29:00 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-03 09:29:41 +0100 |
| commit | 8ee558d8041f3facc79a13242c624c2ca87626e7 (patch) | |
| tree | b13d19af4fb40b1ab63d6f5cb94dcfa5f5c54d78 /drivers/gpu/drm/i915 | |
| parent | 2c623c11c7d87ada0121c5502358b30c9a849d2d (diff) | |
| download | talos-op-linux-8ee558d8041f3facc79a13242c624c2ca87626e7.tar.gz talos-op-linux-8ee558d8041f3facc79a13242c624c2ca87626e7.zip | |
drm/i915/skl: Update in Gen9 multi-engine forcewake range
Updates in forcewake range for Render/Media/Common
power wells for Gen9.
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Zhe Wang <zhe1.wang@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_uncore.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 2b34c046da66..46de8d75b4bf 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -671,18 +671,22 @@ void assert_force_wake_inactive(struct drm_i915_private *dev_priv) REG_RANGE((reg), 0x22000, 0x24000)) #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ - REG_RANGE((reg), 0xC00, 0x2000) + REG_RANGE((reg), 0xB00, 0x2000) #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ - (REG_RANGE((reg), 0x2000, 0x4000) || \ + (REG_RANGE((reg), 0x2000, 0x2700) || \ + REG_RANGE((reg), 0x3000, 0x4000) || \ REG_RANGE((reg), 0x5200, 0x8000) || \ + REG_RANGE((reg), 0x8140, 0x8160) || \ REG_RANGE((reg), 0x8300, 0x8500) || \ REG_RANGE((reg), 0x8C00, 0x8D00) || \ REG_RANGE((reg), 0xB000, 0xB480) || \ - REG_RANGE((reg), 0xE000, 0xE800)) + REG_RANGE((reg), 0xE000, 0xE900) || \ + REG_RANGE((reg), 0x24400, 0x24800)) #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ - (REG_RANGE((reg), 0x8800, 0x8A00) || \ + (REG_RANGE((reg), 0x8130, 0x8140) || \ + REG_RANGE((reg), 0x8800, 0x8A00) || \ REG_RANGE((reg), 0xD000, 0xD800) || \ REG_RANGE((reg), 0x12000, 0x14000) || \ REG_RANGE((reg), 0x1A000, 0x1EA00) || \ |
