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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2013-10-11 12:09:29 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-11 23:32:32 +0200 |
| commit | e8cde23b4607e19bd079a8173393a0d16aadfe31 (patch) | |
| tree | 9662095e3f5b0f6854efd3d94851ca0e652d9c79 /drivers/gpu/drm/i915/intel_sideband.c | |
| parent | fbf49ea21bd4f2ed88d678f7fc8b34a7dd0a7460 (diff) | |
| download | talos-op-linux-e8cde23b4607e19bd079a8173393a0d16aadfe31.tar.gz talos-op-linux-e8cde23b4607e19bd079a8173393a0d16aadfe31.zip | |
drm/i915: don't save/restore CACHE_MODE_0 on gen7+
On gen7+, CACHE_MODE_0 moved, so we're clobbering some other reg rather
than restoring CACHE_MODE_0. Don't do that.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sideband.c')
0 files changed, 0 insertions, 0 deletions
