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| author | Arun Siluvery <arun.siluvery@linux.intel.com> | 2016-01-18 15:59:36 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2016-01-19 20:37:55 +0100 |
| commit | f3272e7a7456240209e758d6a995acbae1d21e8e (patch) | |
| tree | 3781975c2f4240a1a6c4979a619db9c86e54dbd4 /drivers/gpu/drm/i915/intel_sdvo_regs.h | |
| parent | cbfc2d26ac7364b45fbc6f5790a043c72c8a2230 (diff) | |
| download | talos-op-linux-f3272e7a7456240209e758d6a995acbae1d21e8e.tar.gz talos-op-linux-f3272e7a7456240209e758d6a995acbae1d21e8e.zip | |
drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC
In GuC submission mode, driver has to provide a list of registers to be
save/restored during gpu reset, make the max no. of registers value consistent
with that of the value defined in FW. If they are not in sync then register
save/restore during gpu reset won't work as expected.
Cc: Alex Dai <yu.dai@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453132776-22229-1-git-send-email-arun.siluvery@linux.intel.com
Reviewed-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sdvo_regs.h')
0 files changed, 0 insertions, 0 deletions
