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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-24 14:04:12 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-03 11:18:08 +0200 |
| commit | 6b26c86d615747f67fede6ca9609b0f8b2037d11 (patch) | |
| tree | 5abfc0fecc0549878c0b93fb81e8fa535c1439b6 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | ee7b9f93fd96a72e5d09e2b44024c11880873c6b (diff) | |
| download | talos-op-linux-6b26c86d615747f67fede6ca9609b0f8b2037d11.tar.gz talos-op-linux-6b26c86d615747f67fede6ca9609b0f8b2037d11.zip | |
drm/i915: create macros to handle masked bits
... and put them to so good use.
Note that there's functional change in vlv clock gating code, we now
no longer spuriously read back the current value of the bit. According
to Bspec the high bits should always read zero, so ORing this in
should have no effect.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a2d2ce474d0e..a26bf49c4649 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2821,9 +2821,8 @@ static void valleyview_init_clock_gating(struct drm_device *dev) intel_flush_display_plane(dev_priv, pipe); } - I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) | - (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) | - PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); + I915_WRITE(CACHE_MODE_1, + _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); } static void g4x_init_clock_gating(struct drm_device *dev) |
