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author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-03-31 11:21:57 +0200 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-11 12:16:53 +0200 |
commit | 80e829fade4eea5f07c410df6a551c42e2d0ca9c (patch) | |
tree | c347937e2a2d83b0e9154b33866a0bfdc99251b3 /drivers/gpu/drm/i915/intel_display.c | |
parent | 27c1cbd06a7620b354cbb363834f3bb8df4f410d (diff) | |
download | talos-op-linux-80e829fade4eea5f07c410df6a551c42e2d0ca9c.tar.gz talos-op-linux-80e829fade4eea5f07c410df6a551c42e2d0ca9c.zip |
drm/i915: implement ColorBlt w/a
According to an internal workaround master list, we need to set bit 5
of register 9400 to avoid issues with color blits.
Testing shows that this seems to fix the blitter hangs when fbc is
enabled on snb, thanks to Chris Wilson for figuring this out.
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Michael "brot" Groh <michael.groh@minad.de>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f446e66cbdaf..bae38acf44dc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8556,6 +8556,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); + I915_WRITE(GEN6_UCGCTL1, + I915_READ(GEN6_UCGCTL1) | + GEN6_BLBUNIT_CLOCK_GATE_DISABLE); + /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock * gating disable must be set. Failure to set it results in * flickering pixels due to Z write ordering failures after |