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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-23 18:30:00 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-26 10:24:48 +0200 |
| commit | c9809791ae0ae3e5792fc6ad3d4a5d9658aadc62 (patch) | |
| tree | d45f5cf23c3bb15b0fa3147892a75e28b88d380a /drivers/gpu/drm/i915/intel_ddi.c | |
| parent | 702e7a56af3780d8b3a717f698209bef44187bb0 (diff) | |
| download | talos-op-linux-c9809791ae0ae3e5792fc6ad3d4a5d9658aadc62.tar.gz talos-op-linux-c9809791ae0ae3e5792fc6ad3d4a5d9658aadc62.zip | |
drm/i915: convert PIPE_MSA_MISC to transcoder
Same as the other registers. This one also appeared on Haswell for the
first time, so that's why we are renaming it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ddi.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 4b5366b9b04d..c3d06532e9c5 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -888,32 +888,32 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); - enum pipe pipe = intel_crtc->pipe; + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; int type = intel_encoder->type; uint32_t temp; if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { - temp = PIPE_MSA_SYNC_CLK; + temp = TRANS_MSA_SYNC_CLK; switch (intel_crtc->bpp) { case 18: - temp |= PIPE_MSA_6_BPC; + temp |= TRANS_MSA_6_BPC; break; case 24: - temp |= PIPE_MSA_8_BPC; + temp |= TRANS_MSA_8_BPC; break; case 30: - temp |= PIPE_MSA_10_BPC; + temp |= TRANS_MSA_10_BPC; break; case 36: - temp |= PIPE_MSA_12_BPC; + temp |= TRANS_MSA_12_BPC; break; default: - temp |= PIPE_MSA_8_BPC; - WARN(1, "%d bpp unsupported by pipe DDI function\n", + temp |= TRANS_MSA_8_BPC; + WARN(1, "%d bpp unsupported by DDI function\n", intel_crtc->bpp); } - I915_WRITE(PIPE_MSA_MISC(pipe), temp); + I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); } } |
