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authorAl Viro <viro@zeniv.linux.org.uk>2012-11-16 22:27:58 -0500
committerAl Viro <viro@zeniv.linux.org.uk>2012-11-16 22:27:58 -0500
commitd05f06e60df4f56a70fb8a3e46335b40687169e9 (patch)
treec1eec6749fed86a21b08606e1e4acefe4b033253 /arch/xtensa/kernel/coprocessor.S
parent0af1c5300db31f25a412e6e83d42b1747d56c9de (diff)
parent1d72d9f83df057e71c7951def41138a0230bf737 (diff)
downloadtalos-op-linux-d05f06e60df4f56a70fb8a3e46335b40687169e9.tar.gz
talos-op-linux-d05f06e60df4f56a70fb8a3e46335b40687169e9.zip
Merge branch 'arch-frv' into no-rebases
Diffstat (limited to 'arch/xtensa/kernel/coprocessor.S')
-rw-r--r--arch/xtensa/kernel/coprocessor.S20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S
index 2bc1e145c0a4..54c3be313bfa 100644
--- a/arch/xtensa/kernel/coprocessor.S
+++ b/arch/xtensa/kernel/coprocessor.S
@@ -43,7 +43,7 @@
/* IO protection is currently unsupported. */
ENTRY(fast_io_protect)
- wsr a0, EXCSAVE_1
+ wsr a0, excsave1
movi a0, unrecoverable_exception
callx0 a0
@@ -220,7 +220,7 @@ ENTRY(coprocessor_restore)
*/
ENTRY(fast_coprocessor_double)
- wsr a0, EXCSAVE_1
+ wsr a0, excsave1
movi a0, unrecoverable_exception
callx0 a0
@@ -229,13 +229,13 @@ ENTRY(fast_coprocessor)
/* Save remaining registers a1-a3 and SAR */
- xsr a3, EXCSAVE_1
+ xsr a3, excsave1
s32i a3, a2, PT_AREG3
- rsr a3, SAR
+ rsr a3, sar
s32i a1, a2, PT_AREG1
s32i a3, a2, PT_SAR
mov a1, a2
- rsr a2, DEPC
+ rsr a2, depc
s32i a2, a1, PT_AREG2
/*
@@ -248,17 +248,17 @@ ENTRY(fast_coprocessor)
/* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
- rsr a3, EXCCAUSE
+ rsr a3, exccause
addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
/* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
ssl a3 # SAR: 32 - coprocessor_number
movi a2, 1
- rsr a0, CPENABLE
+ rsr a0, cpenable
sll a2, a2
or a0, a0, a2
- wsr a0, CPENABLE
+ wsr a0, cpenable
rsync
/* Retrieve previous owner. (a3 still holds CP number) */
@@ -291,7 +291,7 @@ ENTRY(fast_coprocessor)
/* Note that only a0 and a1 were preserved. */
-2: rsr a3, EXCCAUSE
+2: rsr a3, exccause
addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
movi a0, coprocessor_owner
addx4 a0, a3, a0
@@ -321,7 +321,7 @@ ENTRY(fast_coprocessor)
l32i a0, a1, PT_SAR
l32i a3, a1, PT_AREG3
l32i a2, a1, PT_AREG2
- wsr a0, SAR
+ wsr a0, sar
l32i a0, a1, PT_AREG0
l32i a1, a1, PT_AREG1
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