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| author | Chris Metcalf <cmetcalf@tilera.com> | 2012-03-27 15:40:20 -0400 |
|---|---|---|
| committer | Chris Metcalf <cmetcalf@tilera.com> | 2012-05-25 12:48:20 -0400 |
| commit | 51007004f44c9588d70ffb77e1f52479bd5b0e37 (patch) | |
| tree | ddf8dd2f83554ecbe9de0c690cfab3889308397b /arch/tile/mm/init.c | |
| parent | 76e10d158efb6d4516018846f60c2ab5501900bc (diff) | |
| download | talos-op-linux-51007004f44c9588d70ffb77e1f52479bd5b0e37.tar.gz talos-op-linux-51007004f44c9588d70ffb77e1f52479bd5b0e37.zip | |
arch/tile: use interrupt critical sections less
In general we want to avoid ever touching memory while within an
interrupt critical section, since the page fault path goes through
a different path from the hypervisor when in an interrupt critical
section, and we carefully decided with tilegx that we didn't need
to support this path in the kernel. (On tilepro we did implement
that path as part of supporting atomic instructions in software.)
In practice we always need to touch the kernel stack, since that's
where we store the interrupt state before releasing the critical
section, but this change cleans up a few things. The IRQ_ENABLE
macro is split up so that when we want to enable interrupts in a
deferred way (e.g. for cpu_idle or for interrupt return) we can
read the per-cpu enable mask before entering the critical section.
The cache-migration code is changed to use interrupt masking instead
of interrupt critical sections. And, the interrupt-entry code is
changed so that we defer loading "tp" from per-cpu data until after
we have released the interrupt critical section.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile/mm/init.c')
| -rw-r--r-- | arch/tile/mm/init.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c index 6a9d20ddc34f..1e4633520b35 100644 --- a/arch/tile/mm/init.c +++ b/arch/tile/mm/init.c @@ -444,6 +444,7 @@ static pgd_t pgtables[PTRS_PER_PGD] */ static void __init kernel_physical_mapping_init(pgd_t *pgd_base) { + unsigned long long irqmask; unsigned long address, pfn; pmd_t *pmd; pte_t *pte; @@ -633,10 +634,13 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base) * - install pgtables[] as the real page table * - flush the TLB so the new page table takes effect */ + irqmask = interrupt_mask_save_mask(); + interrupt_mask_set_mask(-1ULL); rc = flush_and_install_context(__pa(pgtables), init_pgprot((unsigned long)pgtables), __get_cpu_var(current_asid), cpumask_bits(my_cpu_mask)); + interrupt_mask_restore_mask(irqmask); BUG_ON(rc != 0); /* Copy the page table back to the normal swapper_pg_dir. */ |
