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| author | Ingo Molnar <mingo@elte.hu> | 2009-03-28 22:27:45 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-28 22:27:45 +0100 |
| commit | 3fab191002b184e4390aa07c7149c6cc7b638ec7 (patch) | |
| tree | 821382d49e47c19531bfc3bb9e1f8922486374d4 /arch/sh/mm/Kconfig | |
| parent | 93394a761d78503f11d05b1a7b23d5a9ccc8dad2 (diff) | |
| parent | 7c730ccdc1188b97f5c8cb690906242c7ed75c22 (diff) | |
| download | talos-op-linux-3fab191002b184e4390aa07c7149c6cc7b638ec7.tar.gz talos-op-linux-3fab191002b184e4390aa07c7149c6cc7b638ec7.zip | |
Merge branch 'linus' into x86/core
Diffstat (limited to 'arch/sh/mm/Kconfig')
| -rw-r--r-- | arch/sh/mm/Kconfig | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index 555ec9714b9e..10c24356d2d5 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -57,7 +57,7 @@ config 32BIT bool default y if CPU_SH5 -config PMB +config PMB_ENABLE bool "Support 32-bit physical addressing through PMB" depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) select 32BIT @@ -67,6 +67,33 @@ config PMB 32-bits through the SH-4A PMB. If this is not set, legacy 29-bit physical addressing will be used. +choice + prompt "PMB handling type" + depends on PMB_ENABLE + default PMB_FIXED + +config PMB + bool "PMB" + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) + select 32BIT + help + If you say Y here, physical addressing will be extended to + 32-bits through the SH-4A PMB. If this is not set, legacy + 29-bit physical addressing will be used. + +config PMB_FIXED + bool "fixed PMB" + depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \ + CPU_SUBTYPE_SH7785) + select 32BIT + help + If this option is enabled, fixed PMB mappings are inherited + from the boot loader, and the kernel does not attempt dynamic + management. This is the closest to legacy 29-bit physical mode, + and allows systems to support up to 512MiB of system memory. + +endchoice + config X2TLB bool "Enable extended TLB mode" depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL |
