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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-11-09 18:42:35 +0900
committerRalf Baechle <ralf@linux-mips.org>2007-11-15 23:21:50 +0000
commit89becf5c0d9019f4f9300840f08a98ee33d57d37 (patch)
tree8b6a9295e957de54fdad6866c1437f3d48b12be0 /arch/mips/lasat
parentfcee3faf8339bb65660c9a22123f71aa0cc30514 (diff)
downloadtalos-op-linux-89becf5c0d9019f4f9300840f08a98ee33d57d37.tar.gz
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[MIPS] Lasat: Fix overlap of interrupt number ranges.
The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lasat')
-rw-r--r--arch/mips/lasat/interrupt.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index ba9692be3564..cfeab669782f 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -19,17 +19,14 @@
* Lasat boards.
*/
#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
+#include <linux/irq.h>
#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>
#include <asm/lasat/lasatint.h>
-#include <asm/time.h>
-#include <asm/gdb-stub.h>
+
+#include <irq.h>
static volatile int *lasat_int_status;
static volatile int *lasat_int_mask;
@@ -97,12 +94,18 @@ asmlinkage void plat_irq_dispatch(void)
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status) {
- irq = LASATINT_BASE + ls1bit32(int_status);
+ irq = LASAT_IRQ_BASE + ls1bit32(int_status);
do_IRQ(irq);
}
}
+static struct irqaction cascade = {
+ .handler = no_action,
+ .mask = CPU_MASK_NONE,
+ .name = "cascade",
+};
+
void __init arch_init_irq(void)
{
int i;
@@ -127,6 +130,9 @@ void __init arch_init_irq(void)
}
mips_cpu_irq_init();
- for (i = LASATINT_BASE; i <= LASATINT_END; i++)
+
+ for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
+
+ setup_irq(LASAT_CASCADE_IRQ, &cascade);
}
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