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authorManuel Lauss <manuel.lauss@gmail.com>2014-07-23 16:36:48 +0200
committerRalf Baechle <ralf@linux-mips.org>2014-07-30 14:08:42 +0200
commit474402291a0ad4778a4e5fdff6ae507b2a26d809 (patch)
treef1adaa3305c44541325eba5a4c41aac10a176588 /arch/mips/include/asm/mach-au1x00
parent2f73bfbe0873452f4cd388ec2f67f8226fe93f79 (diff)
downloadtalos-op-linux-474402291a0ad4778a4e5fdff6ae507b2a26d809.tar.gz
talos-op-linux-474402291a0ad4778a4e5fdff6ae507b2a26d809.zip
MIPS: Alchemy: clock framework integration of onchip clocks
This patch introduces common clock framework integration for all configurable on-chip clocks on Alchemy chips: - 2 or 3 PLLs which generate integer multiples of the root rate 12MHz, - 6 dividers which take one of the 3 PLLs as input and divide their rate by either multiples of 2 or 1 (Au1300). - another bank of up to 6 muxes which take either one of the 6 above dividers or one of the PLLs directly and divide their rate further by 1, 2, 3 or 4. - a few other sources which are used by onchip peripherals and are informational. This implementation will take the clock tree as it was set up by boot firmware: all in-kernel boards should continue to work without having to set up the clock tree in board code. CLK_IGNORE_DISABLED will be removed once all drivers have been converted. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7466/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 754207071b58..1f40c0a00e57 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -47,6 +47,21 @@
#define ALCHEMY_GPIC_INT_NUM 128
#define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
+/* common clock names, shared among all variants. AUXPLL2 is Au1300 */
+#define ALCHEMY_ROOT_CLK "root_clk"
+#define ALCHEMY_CPU_CLK "cpu_clk"
+#define ALCHEMY_AUXPLL_CLK "auxpll_clk"
+#define ALCHEMY_AUXPLL2_CLK "auxpll2_clk"
+#define ALCHEMY_SYSBUS_CLK "sysbus_clk"
+#define ALCHEMY_PERIPH_CLK "periph_clk"
+#define ALCHEMY_MEM_CLK "mem_clk"
+#define ALCHEMY_LR_CLK "lr_clk"
+#define ALCHEMY_FG0_CLK "fg0_clk"
+#define ALCHEMY_FG1_CLK "fg1_clk"
+#define ALCHEMY_FG2_CLK "fg2_clk"
+#define ALCHEMY_FG3_CLK "fg3_clk"
+#define ALCHEMY_FG4_CLK "fg4_clk"
+#define ALCHEMY_FG5_CLK "fg5_clk"
/* Au1300 peripheral interrupt numbers */
#define AU1300_FIRST_INT (ALCHEMY_GPIC_INT_BASE)
@@ -523,6 +538,7 @@
#define AU1000_SYS_CPUPLL 0x60
#define AU1000_SYS_AUXPLL 0x64
+#define AU1300_SYS_AUXPLL2 0x68
/**********************************************************************/
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