Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (80 commits)
  [MIPS] tlbex.c: Cleanup __init usage.
  [MIPS] WRPPMC serial support move to platform device
  [MIPS] R1: Fix hazard barriers to make kernels work on R2 also.
  [MIPS] VPE: reimplement ELF loader.
  [MIPS] cleanup WRPPMC include files
  [MIPS] Add BUG_ON assertion for attempt to run kernel on the wrong CPU type.
  [MIPS] SMP: Use ISO C struct initializer for local structs.
  [MIPS] SMP: Kill useless casts.
  [MIPS] Kill num_online_cpus() loops.
  [MIPS] SMP: Implement smp_call_function_mask().
  [MIPS] Make facility to convert CPU types to strings generally available.
  [MIPS] Convert list of CPU types from #define to enum.
  [MIPS] Optimize get_unaligned / put_unaligned implementations.
  [MIPS] checkfiles: Fix "need space after that ','" errors.
  [MIPS] Fix "no space between function name and open parenthesis" warnings.
  [MIPS] Allow hardwiring of the CPU type to a single type for optimization.
  [MIPS] tlbex: Size optimize code by declaring a few functions inline.
  [MIPS] pg-r4k.c: Dump the generated code
  [MIPS] Cobalt: Remove cobalt_machine_power_off()
  [MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.c
  ...

1 files changed, 79 insertions, 0 deletions

diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c
new file mode 100644
index 000000000000..f5a53acf995a
--- /dev/null
+++ b/arch/mips/bcm47xx/gpio.c
@@ -0,0 +1,79 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+ */
+
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_driver_chipcommon.h>
+#include <linux/ssb/ssb_driver_extif.h>
+#include <asm/mach-bcm47xx/bcm47xx.h>
+#include <asm/mach-bcm47xx/gpio.h>
+
+int bcm47xx_gpio_to_irq(unsigned gpio)
+{
+	if (ssb_bcm47xx.chipco.dev)
+		return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2;
+	else if (ssb_bcm47xx.extif.dev)
+		return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2;
+	else
+		return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(bcm47xx_gpio_to_irq);
+
+int bcm47xx_gpio_get_value(unsigned gpio)
+{
+	if (ssb_bcm47xx.chipco.dev)
+		return ssb_chipco_gpio_in(&ssb_bcm47xx.chipco, 1 << gpio);
+	else if (ssb_bcm47xx.extif.dev)
+		return ssb_extif_gpio_in(&ssb_bcm47xx.extif, 1 << gpio);
+	else
+		return 0;
+}
+EXPORT_SYMBOL_GPL(bcm47xx_gpio_get_value);
+
+void bcm47xx_gpio_set_value(unsigned gpio, int value)
+{
+	if (ssb_bcm47xx.chipco.dev)
+		ssb_chipco_gpio_out(&ssb_bcm47xx.chipco,
+				    1 << gpio,
+				    value ? 1 << gpio : 0);
+	else if (ssb_bcm47xx.extif.dev)
+		ssb_extif_gpio_out(&ssb_bcm47xx.extif,
+				   1 << gpio,
+				   value ? 1 << gpio : 0);
+}
+EXPORT_SYMBOL_GPL(bcm47xx_gpio_set_value);
+
+int bcm47xx_gpio_direction_input(unsigned gpio)
+{
+	if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
+		ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
+				      1 << gpio, 0);
+	else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
+		ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
+				     1 << gpio, 0);
+	else
+		return -EINVAL;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_input);
+
+int bcm47xx_gpio_direction_output(unsigned gpio, int value)
+{
+	bcm47xx_gpio_set_value(gpio, value);
+
+	if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
+		ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
+				      1 << gpio, 1 << gpio);
+	else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
+		ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
+				     1 << gpio, 1 << gpio);
+	else
+		return -EINVAL;
+	return 0;
+}
+EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
+