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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-10-09 21:31:56 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-09 21:31:56 +0100 |
| commit | 6a4690c22f5da1eb1c898b61b6a80da52fbd976f (patch) | |
| tree | a03891a32abe0da191fb765fe669a597e07423c6 /arch/blackfin/include/asm/cache.h | |
| parent | 90bb28b0644f7324f8bd1feb27b35146e6785ba2 (diff) | |
| parent | 8ec53663d2698076468b3e1edc4e1b418bd54de3 (diff) | |
| download | talos-op-linux-6a4690c22f5da1eb1c898b61b6a80da52fbd976f.tar.gz talos-op-linux-6a4690c22f5da1eb1c898b61b6a80da52fbd976f.zip | |
Merge branch 'ptebits' into devel
Conflicts:
arch/arm/Kconfig
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
| -rw-r--r-- | arch/blackfin/include/asm/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h new file mode 100644 index 000000000000..023d72133b5a --- /dev/null +++ b/arch/blackfin/include/asm/cache.h @@ -0,0 +1,29 @@ +/* + * include/asm-blackfin/cache.h + */ +#ifndef __ARCH_BLACKFIN_CACHE_H +#define __ARCH_BLACKFIN_CACHE_H + +/* + * Bytes per L1 cache line + * Blackfin loads 32 bytes for cache + */ +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +/* + * Put cacheline_aliged data to L1 data memory + */ +#ifdef CONFIG_CACHELINE_ALIGNED_L1 +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data_l1.cacheline_aligned"))) +#endif + +/* + * largest L1 which this arch supports + */ +#define L1_CACHE_SHIFT_MAX 5 + +#endif |
